ENGR00153221 [MX6Q uSDHC]workaround for TC intr coming ealier than DMA intr

if TC interrupt bit is set but DMA interrupt bit is clear, read status register
again in case DMA interrupt will come in next time cycle

Signed-off-by: Tony Lin <tony.lin@freescale.com>

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 3938955c06050f9499ed8d2b97d9b47cc171055c..958a0ed88259dbeff2242304a027a9deb1c9c22a 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -99,6 +99,17 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
                        val |= SDHCI_CARD_PRESENT;
        }
 
+       if (reg == SDHCI_INT_STATUS && cpu_is_mx6q())
+               /*
+                * on mx6q, there is low possibility that
+                * DATA END interrupt comes ealier than DMA
+                * END interrupt which is conflict with standard
+                * host controller spec. In this case, read the
+                * status register again will workaround this issue.
+                */
+               if ((val & SDHCI_INT_DATA_END) && \
+                       !(val & SDHCI_INT_DMA_END))
+                       val = readl(host->ioaddr + reg);
        return val;
 }