if (cam->overlay_on == true)
stop_preview(cam);
- camera_power(cam, false);
+ if (cam->capture_on == true || cam->overlay_on == true)
+ camera_power(cam, false);
return 0;
}
cam->low_power = false;
wake_up_interruptible(&cam->power_queue);
- camera_power(cam, true);
+ if (cam->capture_on == true || cam->overlay_on == true)
+ camera_power(cam, true);
if (cam->overlay_on == true)
start_preview(cam);
void csi_mclk_enable(void)
{
+ clk_enable(&csi_mclk);
__raw_writel(__raw_readl(CSI_CSICR1) | BIT_MCLKEN, CSI_CSICR1);
}
void csi_mclk_disable(void)
{
__raw_writel(__raw_readl(CSI_CSICR1) & ~BIT_MCLKEN, CSI_CSICR1);
+ clk_disable(&csi_mclk);
}
static int __devinit csi_probe(struct platform_device *pdev)
return PTR_ERR(per_clk);
clk_put(per_clk);
+ /*
+ * On mx6sl, there's no divider in CSI module(BIT_MCLKDIV in CSI_CSICR1
+ * is marked as reserved). We use CSI clock in CCM.
+ * However, the value read from BIT_MCLKDIV bits are 0, which is
+ * equivalent to "divider=1". The code works for mx6sl without change.
+ */
csi_mclk.parent = per_clk;
- clk_enable(per_clk);
csi_mclk_recalc(&csi_mclk);
err:
static int __devexit csi_remove(struct platform_device *pdev)
{
- clk_disable(&csi_mclk);
iounmap(csi_regbase);
return 0;