Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull core irq changes from Ingo Molnar:
 "A collection of small fixes."

By Thomas Gleixner
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  hexagon: Remove select of not longer existing Kconfig switches
  arm: Select core options instead of redefining them
  genirq: Do not consider disabled wakeup irqs
  genirq: Allow check_wakeup_irqs to notice level-triggered interrupts
  genirq: Be more informative on irq type mismatch
  genirq: Reject bogus threaded irq requests
  genirq: Streamline irq_action

diff --combined arch/arm/Kconfig
index 4305ae25652be196fa2862eda08f86302818122c,1f516766aed6441acd285e62a05730b574cfb15d..002b1c8da225608dc78c8784c6994dab52d63418
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -11,7 -11,6 +11,7 @@@ config AR
        select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
        select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
        select HAVE_ARCH_KGDB
 +      select HAVE_ARCH_TRACEHOOK
        select HAVE_KPROBES if !XIP_KERNEL
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@@ -31,13 -30,12 +31,15 @@@
        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
        select HAVE_C_RECORDMCOUNT
        select HAVE_GENERIC_HARDIRQS
 +      select HARDIRQS_SW_RESEND
 +      select GENERIC_IRQ_PROBE
        select GENERIC_IRQ_SHOW
+       select GENERIC_IRQ_PROBE
+       select HARDIRQS_SW_RESEND
        select CPU_PM if (SUSPEND || CPU_IDLE)
        select GENERIC_PCI_IOMAP
 -      select HAVE_BPF_JIT if NET
 +      select HAVE_BPF_JIT
 +      select GENERIC_SMP_IDLE_THREAD
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@@ -155,6 -153,9 +157,6 @@@ config ARCH_HAS_CPUFRE
          and that the relevant menu configurations are displayed for
          it.
  
 -config ARCH_HAS_CPU_IDLE_WAIT
 -       def_bool y
 -
  config GENERIC_HWEIGHT
        bool
        default y
@@@ -273,7 -274,6 +275,7 @@@ config ARCH_INTEGRATO
        select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select SPARSE_IRQ
 +      select MULTI_IRQ_HANDLER
        help
          Support for ARM's Integrator platform.
  
@@@ -626,6 -626,7 +628,6 @@@ config ARCH_MM
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
        select GPIO_PXA
 -      select TICK_ONESHOT
        select PLAT_PXA
        select SPARSE_IRQ
        select GENERIC_ALLOCATOR
@@@ -709,6 -710,7 +711,6 @@@ config ARCH_PX
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
        select GPIO_PXA
 -      select TICK_ONESHOT
        select PLAT_PXA
        select SPARSE_IRQ
        select AUTO_ZRELADDR
@@@ -775,6 -777,7 +777,6 @@@ config ARCH_SA110
        select CPU_FREQ
        select GENERIC_CLOCKEVENTS
        select CLKDEV_LOOKUP
 -      select TICK_ONESHOT
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_IDE
        select NEED_MACH_MEMORY_H
@@@ -1177,15 -1180,6 +1179,15 @@@ if !MM
  source "arch/arm/Kconfig-nommu"
  endif
  
 +config ARM_ERRATA_326103
 +      bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 +      depends on CPU_V6
 +      help
 +        Executing a SWP instruction to read-only memory does not set bit 11
 +        of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 +        treat the access as a read, preventing a COW from occurring and
 +        causing the faulting task to livelock.
 +
  config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
        depends on CPU_V6 || CPU_V6K
@@@ -1543,15 -1537,10 +1545,15 @@@ config HAVE_ARM_SC
        help
          This option enables support for the ARM system coherency unit
  
 +config ARM_ARCH_TIMER
 +      bool "Architected timer support"
 +      depends on CPU_V7
 +      help
 +        This option enables support for the ARM architected timer
 +
  config HAVE_ARM_TWD
        bool
        depends on SMP
 -      select TICK_ONESHOT
        help
          This options enables support for the ARM timer and watchdog unit
  

diff --combined arch/hexagon/Kconfig
index d2e4a333033626d8ca1fb9ebf09851dfe54278cd,3126fc68593c55cd77d452c031db0402b59210c0..22615dd022197ee8656d75eabf7fd4ba1ebb1347
--- 1/arch/hexagon/Kconfig
--- 2/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@@ -18,8 -18,6 +18,6 @@@ config HEXAGO
        select GENERIC_ATOMIC64
        select HAVE_PERF_EVENTS
        select HAVE_GENERIC_HARDIRQS
-       select GENERIC_HARDIRQS_NO__DO_IRQ
-       select GENERIC_HARDIRQS_NO_DEPRECATED
        # GENERIC_ALLOCATOR is used by dma_alloc_coherent()
        select GENERIC_ALLOCATOR
        select GENERIC_IRQ_SHOW
@@@ -27,7 -25,6 +25,7 @@@
        select HAVE_ARCH_TRACEHOOK
        select NO_IOPORT
        select GENERIC_IOMAP
 +      select GENERIC_SMP_IDLE_THREAD
        # mostly generic routines, with some accelerated ones
        ---help---
          Qualcomm Hexagon is a processor architecture designed for high

diff --combined kernel/irq/chip.c
index 3914c1e03cfffb2bf5a3ed016ffcb7bf051c92d4,741f83643da66a83bee1900d0b34d63892bf9cbd..fc275e4f629b941ef0905a77bc4b88b8659b3183
--- 1/kernel/irq/chip.c
--- 2/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@@ -379,8 -379,10 +379,10 @@@ handle_level_irq(unsigned int irq, stru
         * If its disabled or no action available
         * keep it masked and get out of here
         */
-       if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data)))
+       if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
+               desc->istate |= IRQS_PENDING;
                goto out_unlock;
+       }
  
        handle_irq_event(desc);
  
@@@ -518,7 -520,6 +520,7 @@@ handle_edge_irq(unsigned int irq, struc
  out_unlock:
        raw_spin_unlock(&desc->lock);
  }
 +EXPORT_SYMBOL(handle_edge_irq);
  
  #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
  /**