ENGR00318063-12: ARM: imx6: enable clocks only after all parent and rate are initialized

This is a forward porting of commit ebf625e1a496 (ENGR00318063-12: ARM:
imx6: enable clocks only after all parent and rate are initialized) from
imx_3.10.y to imx_3.14.y.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 40335998e8d6a88b4da200293fe47273a943a0f2..9633423e7de2c2b6b12d3ad54ffd84eb67268bf7 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -518,14 +518,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
        imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
 
-       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-               imx_clk_prepare_enable(clk[clks_init_on[i]]);
-
-       if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-               imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
-               imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
-       }
-
        /*
         * Let's initially set up CLKO with OSC24M, since this configuration
         * is widely used by imx6q board designs to clock audio codec.
@@ -540,6 +532,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        if (IS_ENABLED(CONFIG_PCI_IMX6))
                imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF]);
 
+       /*
+        * Enable clocks only after both parent and rate are all initialized
+        * as needed
+        */
+       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+               imx_clk_prepare_enable(clk[clks_init_on[i]]);
+
+       if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+               imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
+               imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
+       }
+
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);
 

diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index b1c04eca284102e5e82718b27582a4d7e1dccb6a..06ffb6f7861f8c2b2b5ad0d2e4f6638171329ed9 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -422,6 +422,27 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        /* Ensure the AHB clk is at 132MHz. */
        imx_clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
 
+       /* set perclk to source from OSC 24MHz */
+       imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
+
+       /* Audio-related clocks configuration */
+       imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+
+       /* Configure pxp clocks */
+       imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+       imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
+
+       /* Initialize Video PLLs to valid frequency (650MHz). */
+       imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
+       /* set PLL5 video as lcdif pix parent clock */
+       imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
+                       clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
+
+       /*
+        * Enable clocks only after both parent and rate are all initialized
+        * as needed
+        */
+
        /*
         * Make sure those always on clocks are enabled to maintain the correct
         * usecount and enabling/disabling of parent PLLs.
@@ -434,26 +455,10 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
                imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
        }
 
-       /* set perclk to source from OSC 24MHz */
-       imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
-
-       /* Audio-related clocks configuration */
-       imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
-
-       /* Configure pxp clocks */
-       imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
-       imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
-
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);
 
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
        mxc_timer_init_dt(np);
-
-       /* Initialize Video PLLs to valid frequency (650MHz). */
-       imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
-       /* set PLL5 video as lcdif pix parent clock */
-       imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
-                       clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
 }
 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);

diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index c4ba60ef3203402aa5d2cbf4f50f0bf203538e52..6a57c7b7fd5abd72a70f64573da2c4d1c3624798 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -522,14 +522,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        /* set perclk to from OSC */
        imx_clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_OSC]);
 
-       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
-               imx_clk_prepare_enable(clks[clks_init_on[i]]);
-
-       if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-               imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
-               imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
-       }
-
        /* Set the default 132MHz for EIM module */
        imx_clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
        imx_clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
@@ -585,6 +577,18 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        if (uart_from_osc)
                imx_clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_OSC]);
 
+       /*
+        * Enable clocks only after both parent and rate are all initialized
+        * as needed
+        */
+       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+               imx_clk_prepare_enable(clks[clks_init_on[i]]);
+
+       if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+               imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
+               imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
+       }
+
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);