imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
- for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
- imx_clk_prepare_enable(clk[clks_init_on[i]]);
-
- if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
- imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
- imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
- }
-
/*
* Let's initially set up CLKO with OSC24M, since this configuration
* is widely used by imx6q board designs to clock audio codec.
if (IS_ENABLED(CONFIG_PCI_IMX6))
imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF]);
+ /*
+ * Enable clocks only after both parent and rate are all initialized
+ * as needed
+ */
+ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+ imx_clk_prepare_enable(clk[clks_init_on[i]]);
+
+ if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
+ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
+ }
+
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
/* Ensure the AHB clk is at 132MHz. */
imx_clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
+ /* set perclk to source from OSC 24MHz */
+ imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
+
+ /* Audio-related clocks configuration */
+ imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+
+ /* Configure pxp clocks */
+ imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
+ imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
+
+ /* Initialize Video PLLs to valid frequency (650MHz). */
+ imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
+ /* set PLL5 video as lcdif pix parent clock */
+ imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
+ clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
+
+ /*
+ * Enable clocks only after both parent and rate are all initialized
+ * as needed
+ */
+
/*
* Make sure those always on clocks are enabled to maintain the correct
* usecount and enabling/disabling of parent PLLs.
imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
}
- /* set perclk to source from OSC 24MHz */
- imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
-
- /* Audio-related clocks configuration */
- imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
-
- /* Configure pxp clocks */
- imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
- imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
-
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
mxc_timer_init_dt(np);
-
- /* Initialize Video PLLs to valid frequency (650MHz). */
- imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
- /* set PLL5 video as lcdif pix parent clock */
- imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
- clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
}
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
/* set perclk to from OSC */
imx_clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_OSC]);
- for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
- imx_clk_prepare_enable(clks[clks_init_on[i]]);
-
- if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
- imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
- imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
- }
-
/* Set the default 132MHz for EIM module */
imx_clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
imx_clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
if (uart_from_osc)
imx_clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_OSC]);
+ /*
+ * Enable clocks only after both parent and rate are all initialized
+ * as needed
+ */
+ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+ imx_clk_prepare_enable(clks[clks_init_on[i]]);
+
+ if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+ imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
+ imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
+ }
+
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);