]> git.karo-electronics.de Git - linux-beck.git/commitdiff
fsl/pci: The new pci suspend/resume implementation
authorWang Dongsheng <dongsheng.wang@freescale.com>
Thu, 20 Mar 2014 03:19:37 +0000 (11:19 +0800)
committerScott Wood <scottwood@freescale.com>
Thu, 20 Mar 2014 03:37:44 +0000 (22:37 -0500)
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.

When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.

So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.

Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
17 files changed:
arch/powerpc/platforms/85xx/c293pcie.c
arch/powerpc/platforms/85xx/corenet_generic.c
arch/powerpc/platforms/85xx/ge_imp3a.c
arch/powerpc/platforms/85xx/mpc8536_ds.c
arch/powerpc/platforms/85xx/mpc85xx_cds.c
arch/powerpc/platforms/85xx/mpc85xx_ds.c
arch/powerpc/platforms/85xx/mpc85xx_mds.c
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
arch/powerpc/platforms/85xx/p1010rdb.c
arch/powerpc/platforms/85xx/p1022_ds.c
arch/powerpc/platforms/85xx/p1022_rdk.c
arch/powerpc/platforms/85xx/p1023_rds.c
arch/powerpc/platforms/85xx/qemu_e500.c
arch/powerpc/platforms/85xx/sbc8548.c
arch/powerpc/platforms/85xx/xes_mpc85xx.c
arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pci.h

index 213d5b8158270058cc41ed6513a8d55d7028baf0..84476b646005aab57db2447ad0f711595bf3d0bf 100644 (file)
@@ -68,6 +68,7 @@ define_machine(c293_pcie) {
        .init_IRQ               = c293_pcie_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index a8877c4e10ad8b425b823e3e3dcece5de7a1c9cc..8e4b1e1a49113cb17b6bf394d743a57bce9e9113 100644 (file)
@@ -179,6 +179,7 @@ define_machine(corenet_generic) {
        .init_IRQ               = corenet_gen_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_coreint_irq,
        .restart                = fsl_rstcr_restart,
index e6285ae6f4239d5e12ada123c937c272964f4e67..11790e074c8a6afd6d513d89617ed25f6771240a 100644 (file)
@@ -215,6 +215,7 @@ define_machine(ge_imp3a) {
        .show_cpuinfo           = ge_imp3a_show_cpuinfo,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index 15ce4b55f117896b2f96cd3dd0bab994a8310613..a378ba3519e9fdb6a830a3e89d0364048e278196 100644 (file)
@@ -76,6 +76,7 @@ define_machine(mpc8536_ds) {
        .init_IRQ               = mpc8536_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index 7a31a0e1df2987b0bf33bd33c90b971676c57f5e..b0753e2220862cb1585fefa23aee64889390b4d3 100644 (file)
@@ -385,6 +385,7 @@ define_machine(mpc85xx_cds) {
 #ifdef CONFIG_PCI
        .restart        = mpc85xx_cds_restart,
        .pcibios_fixup_bus      = mpc85xx_cds_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #else
        .restart        = fsl_rstcr_restart,
 #endif
index 9ebb91ed96a332e1683ec364f3e7ba2a5e0cd982..ffdf02121a7cb9ecf51d888cf26126a621faa4c4 100644 (file)
@@ -209,6 +209,7 @@ define_machine(mpc8544_ds) {
        .init_IRQ               = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -223,6 +224,7 @@ define_machine(mpc8572_ds) {
        .init_IRQ               = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -237,6 +239,7 @@ define_machine(p2020_ds) {
        .init_IRQ               = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index 3c190b4674606deda6def8032a639f1c7a014d64..a392e94a07fadb48413d4f284d62c8a277427a68 100644 (file)
@@ -392,6 +392,7 @@ define_machine(mpc8568_mds) {
        .progress       = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
 
@@ -413,6 +414,7 @@ define_machine(mpc8569_mds) {
        .progress       = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
 
@@ -435,6 +437,7 @@ define_machine(p1021_mds) {
        .progress       = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
 
index 294b179b358465d31d945a2112e510b46531d6b9..e358bed66d014781056f9af672b5171310d5c2f8 100644 (file)
@@ -231,6 +231,7 @@ define_machine(p2020_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -245,6 +246,7 @@ define_machine(p1020_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -259,6 +261,7 @@ define_machine(p1021_rdb_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -273,6 +276,7 @@ define_machine(p2020_rdb_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -287,6 +291,7 @@ define_machine(p1025_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -301,6 +306,7 @@ define_machine(p1020_mbg_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -315,6 +321,7 @@ define_machine(p1020_utm_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -329,6 +336,7 @@ define_machine(p1020_rdb_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -343,6 +351,7 @@ define_machine(p1020_rdb_pd) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -357,6 +366,7 @@ define_machine(p1024_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index d6a3dd3114945676eb89fa4e3e3d91a34a0b1c6c..ad1a3d438a9ee65eb705fe107fdd7283a017d18b 100644 (file)
@@ -78,6 +78,7 @@ define_machine(p1010_rdb) {
        .init_IRQ               = p1010_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index e611e79f23ce68053d0c4190adf2b2104862e6a9..6ac986d3f8a39984ae8308a092191831c796e21b 100644 (file)
@@ -567,6 +567,7 @@ define_machine(p1022_ds) {
        .init_IRQ               = p1022_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index 8c9297112b30d65ddbe8cf6ef8473ded29d74cf8..7a180f0308d55ad316a74c39083515fb92322326 100644 (file)
@@ -147,6 +147,7 @@ define_machine(p1022_rdk) {
        .init_IRQ               = p1022_rdk_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index 2ae9d490c3d940954ac2a805ca14764b5c5bf4d8..0e614007acfb36e7f6fdad6fb139dc2f0ff5e96b 100644 (file)
@@ -126,6 +126,7 @@ define_machine(p1023_rds) {
        .progress               = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
 
@@ -140,5 +141,6 @@ define_machine(p1023_rdb) {
        .progress               = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
index 5cefc5a9a144fa682a69c4499f5ca3802b7a1c6b..7f26732935496381f92446600f30262dccb4215a 100644 (file)
@@ -66,6 +66,7 @@ define_machine(qemu_e500) {
        .init_IRQ               = qemu_e500_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_coreint_irq,
        .restart                = fsl_rstcr_restart,
index f62121825914d952add0d638adfc470551e6e0da..b07214666d65f70a9cf2015bf5dd6264631e6795 100644 (file)
@@ -135,6 +135,7 @@ define_machine(sbc8548) {
        .restart        = fsl_rstcr_restart,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .calibrate_decr = generic_calibrate_decr,
        .progress       = udbg_progress,
index dcbf7e42dce79100881ac66ea4ab93e9a8b5571c..1a9c1085855fea67a08da7f18a3e42793183ff94 100644 (file)
@@ -170,6 +170,7 @@ define_machine(xes_mpc8572) {
        .init_IRQ               = xes_mpc85xx_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -184,6 +185,7 @@ define_machine(xes_mpc8548) {
        .init_IRQ               = xes_mpc85xx_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -198,6 +200,7 @@ define_machine(xes_mpc8540) {
        .init_IRQ               = xes_mpc85xx_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+       .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
index 8cdd344825751a8581059792d3ab5919c69bb463..3f415e252ea54fc34e8dee84ea7de1b56fd54ec1 100644 (file)
 #include <linux/delay.h>
 #include <linux/string.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/bootmem.h>
 #include <linux/memblock.h>
 #include <linux/log2.h>
 #include <linux/slab.h>
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
 #include <linux/uaccess.h>
 
 #include <asm/io.h>
@@ -1094,55 +1097,171 @@ void fsl_pci_assign_primary(void)
        }
 }
 
-static int fsl_pci_probe(struct platform_device *pdev)
+#ifdef CONFIG_PM_SLEEP
+static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
 {
-       int ret;
-       struct device_node *node;
+       struct pci_controller *hose = dev_id;
+       struct ccsr_pci __iomem *pci = hose->private_data;
+       u32 dr;
 
-       node = pdev->dev.of_node;
-       ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
+       dr = in_be32(&pci->pex_pme_mes_dr);
+       if (!dr)
+               return IRQ_NONE;
 
-       mpc85xx_pci_err_probe(pdev);
+       out_be32(&pci->pex_pme_mes_dr, dr);
 
-       return 0;
+       return IRQ_HANDLED;
 }
 
-#ifdef CONFIG_PM
-static int fsl_pci_resume(struct device *dev)
+static int fsl_pci_pme_probe(struct pci_controller *hose)
 {
-       struct pci_controller *hose;
-       struct resource pci_rsrc;
+       struct ccsr_pci __iomem *pci;
+       struct pci_dev *dev;
+       int pme_irq;
+       int res;
+       u16 pms;
 
-       hose = pci_find_hose_for_OF_device(dev->of_node);
-       if (!hose)
-               return -ENODEV;
+       /* Get hose's pci_dev */
+       dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
+
+       /* PME Disable */
+       pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
+       pms &= ~PCI_PM_CTRL_PME_ENABLE;
+       pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
+
+       pme_irq = irq_of_parse_and_map(hose->dn, 0);
+       if (!pme_irq) {
+               dev_err(&dev->dev, "Failed to map PME interrupt.\n");
+
+               return -ENXIO;
+       }
+
+       res = devm_request_irq(hose->parent, pme_irq,
+                       fsl_pci_pme_handle,
+                       IRQF_SHARED,
+                       "[PCI] PME", hose);
+       if (res < 0) {
+               dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq);
+               irq_dispose_mapping(pme_irq);
 
-       if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
-               dev_err(dev, "Get pci register base failed.");
                return -ENODEV;
        }
 
-       setup_pci_atmu(hose);
+       pci = hose->private_data;
+
+       /* Enable PTOD, ENL23D & EXL23D */
+       out_be32(&pci->pex_pme_mes_disr, 0);
+       setbits32(&pci->pex_pme_mes_disr,
+                 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+
+       out_be32(&pci->pex_pme_mes_ier, 0);
+       setbits32(&pci->pex_pme_mes_ier,
+                 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+
+       /* PME Enable */
+       pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
+       pms |= PCI_PM_CTRL_PME_ENABLE;
+       pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
 
        return 0;
 }
 
-static const struct dev_pm_ops pci_pm_ops = {
-       .resume = fsl_pci_resume,
-};
+static void send_pme_turnoff_message(struct pci_controller *hose)
+{
+       struct ccsr_pci __iomem *pci = hose->private_data;
+       u32 dr;
+       int i;
 
-#define PCI_PM_OPS (&pci_pm_ops)
+       /* Send PME_Turn_Off Message Request */
+       setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
 
-#else
+       /* Wait trun off done */
+       for (i = 0; i < 150; i++) {
+               dr = in_be32(&pci->pex_pme_mes_dr);
+               if (dr) {
+                       out_be32(&pci->pex_pme_mes_dr, dr);
+                       break;
+               }
 
-#define PCI_PM_OPS NULL
+               udelay(1000);
+       }
+}
 
+static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
+{
+       send_pme_turnoff_message(hose);
+}
+
+static int fsl_pci_syscore_suspend(void)
+{
+       struct pci_controller *hose, *tmp;
+
+       list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
+               fsl_pci_syscore_do_suspend(hose);
+
+       return 0;
+}
+
+static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
+{
+       struct ccsr_pci __iomem *pci = hose->private_data;
+       u32 dr;
+       int i;
+
+       /* Send Exit L2 State Message */
+       setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
+
+       /* Wait exit done */
+       for (i = 0; i < 150; i++) {
+               dr = in_be32(&pci->pex_pme_mes_dr);
+               if (dr) {
+                       out_be32(&pci->pex_pme_mes_dr, dr);
+                       break;
+               }
+
+               udelay(1000);
+       }
+
+       setup_pci_atmu(hose);
+}
+
+static void fsl_pci_syscore_resume(void)
+{
+       struct pci_controller *hose, *tmp;
+
+       list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
+               fsl_pci_syscore_do_resume(hose);
+}
+
+static struct syscore_ops pci_syscore_pm_ops = {
+       .suspend = fsl_pci_syscore_suspend,
+       .resume = fsl_pci_syscore_resume,
+};
 #endif
 
+void fsl_pcibios_fixup_phb(struct pci_controller *phb)
+{
+#ifdef CONFIG_PM_SLEEP
+       fsl_pci_pme_probe(phb);
+#endif
+}
+
+static int fsl_pci_probe(struct platform_device *pdev)
+{
+       struct device_node *node;
+       int ret;
+
+       node = pdev->dev.of_node;
+       ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
+
+       mpc85xx_pci_err_probe(pdev);
+
+       return 0;
+}
+
 static struct platform_driver fsl_pci_driver = {
        .driver = {
                .name = "fsl-pci",
-               .pm = PCI_PM_OPS,
                .of_match_table = pci_ids,
        },
        .probe = fsl_pci_probe,
@@ -1150,6 +1269,9 @@ static struct platform_driver fsl_pci_driver = {
 
 static int __init fsl_pci_init(void)
 {
+#ifdef CONFIG_PM_SLEEP
+       register_syscore_ops(&pci_syscore_pm_ops);
+#endif
        return platform_driver_register(&fsl_pci_driver);
 }
 arch_initcall(fsl_pci_init);
index 8d455df584711c84c004468be1656fd4b55e36eb..c1cec771d5eae2f7f81381782dbff1193d21db46 100644 (file)
@@ -32,6 +32,13 @@ struct platform_device;
 #define PIWAR_WRITE_SNOOP      0x00005000
 #define PIWAR_SZ_MASK          0x0000003f
 
+#define PEX_PMCR_PTOMR         0x1
+#define PEX_PMCR_EXL2S         0x2
+
+#define PME_DISR_EN_PTOD       0x00008000
+#define PME_DISR_EN_ENL23D     0x00002000
+#define PME_DISR_EN_EXL23D     0x00001000
+
 /* PCI/PCI Express outbound window reg */
 struct pci_outbound_window_regs {
        __be32  potar;  /* 0x.0 - Outbound translation address register */
@@ -111,6 +118,7 @@ struct ccsr_pci {
 
 extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
+extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
 extern int mpc83xx_add_bridge(struct device_node *dev);
 u64 fsl_pci_immrbar_base(struct pci_controller *hose);