]> git.karo-electronics.de Git - karo-tx-uboot.git/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot-atmel
authorTom Rini <trini@konsulko.com>
Mon, 30 Nov 2015 23:13:10 +0000 (18:13 -0500)
committerTom Rini <trini@konsulko.com>
Mon, 30 Nov 2015 23:13:10 +0000 (18:13 -0500)
24 files changed:
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/armv7/Makefile
arch/arm/mach-at91/armv7/sama5d2_devices.c [new file with mode: 0644]
arch/arm/mach-at91/armv7/sama5d4_devices.c
arch/arm/mach-at91/atmel_sfr.c [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91_pmc.h
arch/arm/mach-at91/include/mach/atmel_pio4.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/atmel_usba_udc.h
arch/arm/mach-at91/include/mach/hardware.h
arch/arm/mach-at91/include/mach/sama5_sfr.h
arch/arm/mach-at91/include/mach/sama5d2.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/sama5d4.h
arch/arm/mach-at91/matrix.c [new file with mode: 0644]
board/atmel/sama5d2_xplained/Kconfig [new file with mode: 0644]
board/atmel/sama5d2_xplained/MAINTAINERS [new file with mode: 0644]
board/atmel/sama5d2_xplained/Makefile [new file with mode: 0644]
board/atmel/sama5d2_xplained/sama5d2_xplained.c [new file with mode: 0644]
configs/sama5d2_xplained_mmc_defconfig [new file with mode: 0644]
configs/sama5d2_xplained_spiflash_defconfig [new file with mode: 0644]
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/atmel_pio4.c [new file with mode: 0644]
include/configs/sama5d2_xplained.h [new file with mode: 0644]

index fdaf3287220662e1da8170adeeed48d83def8cf7..c33364758bdb17f4aa415a9fd124d8d498d22e9d 100644 (file)
@@ -71,6 +71,10 @@ config TARGET_AT91SAM9X5EK
        select CPU_ARM926EJS
        select SUPPORT_SPL
 
+config TARGET_SAMA5D2_XPLAINED
+       bool "SAMA5D2 Xplained board"
+       select CPU_V7
+
 config TARGET_SAMA5D3_XPLAINED
        bool "SAMA5D3 Xplained board"
        select CPU_V7
@@ -123,6 +127,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
 source "board/atmel/at91sam9n12ek/Kconfig"
 source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_xplained/Kconfig"
 source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
 source "board/atmel/sama5d4_xplained/Kconfig"
index 30f2b49b69de1d98def023b88c83fe45ffdef4be..5b89617623e7ed7771124e6b1ab399d9f7b47f9e 100644 (file)
@@ -10,7 +10,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
+obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
 endif
 
index f4f35a4bc1923ac59b700925b1ac6fcba66050db..9538bc1fad2a536ec28eceff761a7bbcbe9c7e5c 100644 (file)
@@ -8,6 +8,7 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+obj-$(CONFIG_SAMA5D2)  += sama5d2_devices.o
 obj-$(CONFIG_SAMA5D3)  += sama5d3_devices.o
 obj-$(CONFIG_SAMA5D4)  += sama5d4_devices.o
 obj-y += clock.o
diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c
new file mode 100644 (file)
index 0000000..88f8f2c
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *                   Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d2.h>
+
+char *get_cpu_name()
+{
+       unsigned int extension_id = get_extension_chip_id();
+
+       if (cpu_is_sama5d2()) {
+               switch (extension_id) {
+               case ARCH_EXID_SAMA5D21CU:
+                       return "SAMA5D21";
+               case ARCH_EXID_SAMA5D22CU:
+                       return "SAMA5D22-CU";
+               case ARCH_EXID_SAMA5D22CN:
+                       return "SAMA5D22-CN";
+               case ARCH_EXID_SAMA5D23CU:
+                       return "SAMA5D23-CU";
+               case ARCH_EXID_SAMA5D24CX:
+                       return "SAMA5D24-CX";
+               case ARCH_EXID_SAMA5D24CU:
+                       return "SAMA5D24-CU";
+               case ARCH_EXID_SAMA5D26CU:
+                       return "SAMA5D26-CU";
+               case ARCH_EXID_SAMA5D27CU:
+                       return "SAMA5D27-CU";
+               case ARCH_EXID_SAMA5D27CN:
+                       return "SAMA5D27-CN";
+               case ARCH_EXID_SAMA5D28CU:
+                       return "SAMA5D28-CU";
+               case ARCH_EXID_SAMA5D28CN:
+                       return "SAMA5D28-CN";
+               }
+       }
+
+       return "Unknown CPU type";
+}
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+void at91_udp_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+
+       at91_periph_clk_enable(ATMEL_ID_UDPHS);
+}
+#endif
index 76301d63021b9256e034b3177198d6f2f0910564..ce33cd4988885c76a8432cd683e95041828c6e0e 100644 (file)
@@ -10,7 +10,6 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/sama5_matrix.h>
 #include <asm/arch/sama5_sfr.h>
 #include <asm/arch/sama5d4.h>
 
@@ -46,57 +45,3 @@ void at91_udp_hw_init(void)
        at91_periph_clk_enable(ATMEL_ID_UDPHS);
 }
 #endif
-
-#ifdef CONFIG_SPL_BUILD
-void matrix_init(void)
-{
-       struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
-       struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
-       int i;
-
-       /* Disable the write protect */
-       writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-       writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
-       /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
-       for (i = 4; i <= 10; i++) {
-               writel(0x000f0f0f, &h64mx->ssr[i]);
-               writel(0x0000ffff, &h64mx->sassr[i]);
-               writel(0x0000000f, &h64mx->srtsr[i]);
-       }
-
-       /* CS3 */
-       writel(0x00c0c0c0, &h32mx->ssr[3]);
-       writel(0xff000000, &h32mx->sassr[3]);
-       writel(0xff000000, &h32mx->srtsr[3]);
-
-       /* NFC SRAM */
-       writel(0x00010101, &h32mx->ssr[4]);
-       writel(0x00000001, &h32mx->sassr[4]);
-       writel(0x00000001, &h32mx->srtsr[4]);
-
-       /* Configure Programmable Security peripherals on matrix 64 */
-       writel(readl(&h64mx->spselr[0]) | 0x00080000, &h64mx->spselr[0]);
-       writel(readl(&h64mx->spselr[1]) | 0x00180000, &h64mx->spselr[1]);
-       writel(readl(&h64mx->spselr[2]) | 0x00000008, &h64mx->spselr[2]);
-
-       /* Configure Programmable Security peripherals on matrix 32 */
-       writel(readl(&h32mx->spselr[0]) | 0xFFC00000, &h32mx->spselr[0]);
-       writel(readl(&h32mx->spselr[1]) | 0x60E3FFFF, &h32mx->spselr[1]);
-
-       /* Enable the write protect */
-       writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-       writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-}
-
-void redirect_int_from_saic_to_aic(void)
-{
-       struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
-       u32 key32;
-
-       if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
-               key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
-               writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
-       }
-}
-#endif
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c
new file mode 100644 (file)
index 0000000..2bccb84
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *                   Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_sfr.h>
+
+void redirect_int_from_saic_to_aic(void)
+{
+       struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+       u32 key32;
+
+       if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
+               key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
+               writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
+       }
+}
index 5a51be6288275888d55aad00601474d4a69db4f6..3f50f7718ff5ce6b2c34828001bd883b91572661 100644 (file)
@@ -78,7 +78,8 @@ typedef struct at91_pmc {
 #define AT91_PMC_PLLXR_DIV(x)          (x & 0xFF)
 #define AT91_PMC_PLLXR_PLLCOUNT(x)     ((x & 0x3F) << 8)
 #define AT91_PMC_PLLXR_OUT(x)          ((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+       defined(CONFIG_SAMA5D4)
 #define AT91_PMC_PLLXR_MUL(x)          ((x & 0x7F) << 18)
 #else
 #define AT91_PMC_PLLXR_MUL(x)          ((x & 0x7FF) << 16)
@@ -97,7 +98,8 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_PLLB         0x00000003
 #define AT91_PMC_MCKR_CSS_MASK         0x00000003
 
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+       defined(CONFIG_SAMA5D4) || \
        defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_PRES_1           0x00000000
 #define AT91_PMC_MCKR_PRES_2           0x00000010
@@ -127,10 +129,7 @@ typedef struct at91_pmc {
 #else
 #define AT91_PMC_MCKR_MDIV_1           0x00000000
 #define AT91_PMC_MCKR_MDIV_2           0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-       defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_MDIV_3           0x00000300
-#endif
 #define AT91_PMC_MCKR_MDIV_4           0x00000200
 #define AT91_PMC_MCKR_MDIV_MASK                0x00000300
 #endif
diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h
new file mode 100644 (file)
index 0000000..8bb4b12
--- /dev/null
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation.
+ *                   Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ATMEL_PIO4_H
+#define __ATMEL_PIO4_H
+
+#ifndef __ASSEMBLY__
+
+struct atmel_pio4_port {
+       u32 mskr;               /* 0x00 PIO Mask Register */
+       u32 cfgr;               /* 0x04 PIO Configuration Register */
+       u32 pdsr;               /* 0x08 PIO Pin Data Status Register */
+       u32 locksr;             /* 0x0C PIO Lock Status Register */
+       u32 sodr;               /* 0x10 PIO Set Output Data Register */
+       u32 codr;               /* 0x14 PIO Clear Output Data Register */
+       u32 odsr;               /* 0x18 PIO Output Data Status Register */
+       u32 reserved0;
+       u32 ier;                /* 0x20 PIO Interrupt Enable Register */
+       u32 idr;                /* 0x24 PIO Interrupt Disable Register */
+       u32 imr;                /* 0x28 PIO Interrupt Mask Register */
+       u32 isr;                /* 0x2C PIO Interrupt Status Register */
+       u32 reserved1[3];
+       u32 iofr;               /* 0x3C PIO I/O Freeze Register */
+};
+
+#endif
+
+#define AT91_PIO_PORTA         0x0
+#define AT91_PIO_PORTB         0x1
+#define AT91_PIO_PORTC         0x2
+#define AT91_PIO_PORTD         0x3
+
+int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value);
+int atmel_pio4_get_pio_input(u32 port, u32 pin);
+
+#endif
index 38b5012fce5cc17b828310b9c352677ab5bba060..46a329b1526676a6f12b42acf07889a95262177f 100644 (file)
@@ -31,7 +31,8 @@ static struct usba_ep_data usba_udc_ep[] = {
        EP("ep5", 5, 1024, 3, 1, 1),
        EP("ep6", 6, 1024, 3, 1, 1),
 };
-#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#elif defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+       defined(CONFIG_SAMA5D4)
 static struct usba_ep_data usba_udc_ep[] = {
        EP("ep0", 0, 64, 1, 0, 0),
        EP("ep1", 1, 1024, 3, 1, 0),
index ff6b71b13575814fbd86e105e367f84be2f73f1f..38abfda84eebb3afc007cc28f460d3434bcbadf7 100644 (file)
@@ -23,6 +23,8 @@
 # include <asm/arch/at91sam9g45.h>
 #elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
 # include <asm/arch/at91sam9x5.h>
+#elif defined(CONFIG_SAMA5D2)
+# include <asm/arch/sama5d2.h>
 #elif defined(CONFIG_SAMA5D3)
 # include <asm/arch/sama5d3.h>
 #elif defined(CONFIG_SAMA5D4)
index 3081d3757186c10332c7da43c5cc59af5993d4f4..7b19a20a4e011c22bdf57f8fb1f5d081a6ff60c1 100644 (file)
@@ -32,7 +32,6 @@ struct atmel_sfr {
 #define ATMEL_SFR_DDRCFG_FDQSIEN       0x00020000
 
 /* Bit field in AICREDIR */
-#define ATMEL_SFR_AICREDIR_KEY         0x5F67B102
 #define ATMEL_SFR_AICREDIR_NSAIC       0x00000001
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
new file mode 100644 (file)
index 0000000..c85571c
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ * Chip-specific header file for the SAMA5D2 SoC
+ *
+ * Copyright (C) 2015 Atmel
+ *                   Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __SAMA5D2_H
+#define __SAMA5D2_H
+
+/*
+ * definitions to be used in other places
+ */
+#define CONFIG_AT91FAMILY      /* It's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ           0       /* FIQ Interrupt ID */
+/* 1 */
+#define ATMEL_ID_ARM           2       /* Performance Monitor Unit */
+#define ATMEL_ID_PIT           3       /* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT           4       /* Watchdog Timer Interrupt */
+#define ATMEL_ID_GMAC          5       /* Ethernet MAC */
+#define ATMEL_ID_XDMAC0                6       /* DMA Controller 0 */
+#define ATMEL_ID_XDMAC1                7       /* DMA Controller 1 */
+#define ATMEL_ID_ICM           8       /* Integrity Check Monitor */
+#define ATMEL_ID_AES           9       /* Advanced Encryption Standard */
+#define ATMEL_ID_AESB          10      /* AES bridge */
+#define ATMEL_ID_TDES          11      /* Triple Data Encryption Standard */
+#define ATMEL_ID_SHA           12      /* SHA Signature */
+#define ATMEL_ID_MPDDRC                13      /* MPDDR Controller */
+#define ATMEL_ID_MATRIX1       14      /* H32MX, 32-bit AHB Matrix */
+#define ATMEL_ID_MATRIX0       15      /* H64MX, 64-bit AHB Matrix */
+#define ATMEL_ID_SECUMOD       16      /* Secure Module */
+#define ATMEL_ID_HSMC          17      /* Multi-bit ECC interrupt */
+#define ATMEL_ID_PIOA          18      /* Parallel I/O Controller A */
+#define ATMEL_ID_FLEXCOM0      19      /* FLEXCOM0 */
+#define ATMEL_ID_FLEXCOM1      20      /* FLEXCOM1 */
+#define ATMEL_ID_FLEXCOM2      21      /* FLEXCOM2 */
+#define ATMEL_ID_FLEXCOM3      22      /* FLEXCOM3 */
+#define ATMEL_ID_FLEXCOM4      23      /* FLEXCOM4 */
+#define ATMEL_ID_UART0         24      /* UART0 */
+#define ATMEL_ID_UART1         25      /* UART1 */
+#define ATMEL_ID_UART2         26      /* UART2 */
+#define ATMEL_ID_UART3         27      /* UART3 */
+#define ATMEL_ID_UART4         28      /* UART4 */
+#define ATMEL_ID_TWIHS0                29      /* Two-wire Interface 0 */
+#define ATMEL_ID_TWIHS1                30      /* Two-wire Interface 1 */
+#define ATMEL_ID_SDMMC0                31      /* Secure Data Memory Card Controller 0 */
+#define ATMEL_ID_SDMMC1                32      /* Secure Data Memory Card Controller 1 */
+#define ATMEL_ID_SPI0          33      /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1          34      /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0           35      /* Timer Counter 0 (ch.0,1,2) */
+#define ATMEL_ID_TC1           36      /* Timer Counter 1 (ch.3,4,5) */
+/* 37 */
+#define ATMEL_ID_PWM           38      /* PWMController0 (ch. 0,1,2,3) */
+/* 39 */
+#define ATMEL_ID_ADC           40      /* Touch Screen ADC Controller */
+#define ATMEL_ID_UHPHS         41      /* USB Host High Speed */
+#define ATMEL_ID_UDPHS         42      /* USB Device High Speed */
+#define ATMEL_ID_SSC0          43      /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1          44      /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_LCDC          45      /* LCD Controller */
+#define ATMEL_ID_ISI           46      /* Image Sensor Controller, for A5D2, named after ISC */
+#define ATMEL_ID_TRNG          47      /* True Random Number Generator */
+#define ATMEL_ID_PDMIC         48      /* PDM Interface Controller */
+#define ATMEL_ID_AIC_IRQ       49      /* IRQ Interrupt ID */
+#define ATMEL_ID_SFC           50      /* Fuse Controller */
+#define ATMEL_ID_SECURAM       51      /* Secure RAM */
+#define ATMEL_ID_QSPI0         52      /* QSPI0 */
+#define ATMEL_ID_QSPI1         53      /* QSPI1 */
+#define ATMEL_ID_I2SC0         54      /* Inter-IC Sound Controller 0 */
+#define ATMEL_ID_I2SC1         55      /* Inter-IC Sound Controller 1 */
+#define ATMEL_ID_CAN0_INT0     56      /* MCAN 0 Interrupt0 */
+#define ATMEL_ID_CAN1_INT0     57      /* MCAN 1 Interrupt0 */
+/* 58 */
+#define ATMEL_ID_CLASSD                59      /* Audio Class D Amplifier */
+#define ATMEL_ID_SFR           60      /* Special Function Register */
+#define ATMEL_ID_SAIC          61      /* Secured AIC */
+#define ATMEL_ID_AIC           62      /* Advanced Interrupt Controller */
+#define ATMEL_ID_L2CC          63      /* L2 Cache Controller */
+#define ATMEL_ID_CAN0_INT1     64      /* MCAN 0 Interrupt1 */
+#define ATMEL_ID_CAN1_INT1     65      /* MCAN 1 Interrupt1 */
+#define ATMEL_ID_GMAC_Q1       66      /* GMAC Queue 1 Interrupt */
+#define ATMEL_ID_GMAC_Q2       67      /* GMAC Queue 2 Interrupt */
+#define ATMEL_ID_PIOB          68      /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC          69      /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD          70      /* Parallel I/O Controller D */
+#define ATMEL_ID_SDMMC0_TIMER  71      /* Secure Data Memory Card Controller 0 (TIMER) */
+#define ATMEL_ID_SDMMC1_TIMER  72      /* Secure Data Memory Card Controller 1 (TIMER) */
+/* 73 */
+#define ATMEL_ID_SYS           74      /* System Controller Interrupt */
+#define ATMEL_ID_ACC           75      /* Analog Comparator */
+#define ATMEL_ID_RXLP          76      /* UART Low-Power */
+#define ATMEL_ID_SFRBU         77      /* Special Function Register BackUp */
+#define ATMEL_ID_CHIPID                78      /* Chip ID */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_LCDC                0xf0000000
+#define ATMEL_BASE_XDMAC1      0xf0004000
+#define ATMEL_BASE_MPDDRC      0xf000c000
+#define ATMEL_BASE_XDMAC0      0xf0010000
+#define ATMEL_BASE_PMC         0xf0014000
+#define ATMEL_BASE_QSPI0       0xf0020000
+#define ATMEL_BASE_QSPI1       0xf0024000
+#define ATMEL_BASE_SPI0                0xf8000000
+#define ATMEL_BASE_GMAC                0xf8008000
+#define ATMEL_BASE_TC0         0xf800c000
+#define ATMEL_BASE_TC1         0xf8010000
+#define ATMEL_BASE_HSMC                0xf8014000
+#define ATMEL_BASE_UART0       0xf801c000
+#define ATMEL_BASE_UART1       0xf8020000
+#define ATMEL_BASE_UART2       0xf8024000
+#define ATMEL_BASE_TWI0                0xf8028000
+#define ATMEL_BASE_SYSC                0xf8048000
+#define ATMEL_BASE_SPI1                0xfc000000
+#define ATMEL_BASE_UART3       0xfc008000
+#define ATMEL_BASE_UART4       0xfc00c000
+#define ATMEL_BASE_TWI1                0xfc028000
+#define ATMEL_BASE_UDPHS       0xfc02c000
+
+#define ATMEL_BASE_PIOA                0xfc038000
+
+#define ATMEL_CHIPID_CIDR      0xfc069000
+#define ATMEL_CHIPID_EXID      0xfc069004
+
+/*
+ * Address Memory Space
+ */
+#define ATMEL_BASE_DDRCS               0x20000000
+#define ATMEL_BASE_QSPI0_AES_MEM       0x90000000
+#define ATMEL_BASE_QSPI1_AES_MEM       0x98000000
+#define ATMEL_BASE_SDMMC0              0xa0000000
+#define ATMEL_BASE_SDMMC1              0xb0000000
+#define ATMEL_BASE_QSPI0_MEM           0xd0000000
+#define ATMEL_BASE_QSPI1_MEM           0xd8000000
+
+/*
+ * Internal Memories
+ */
+#define ATMEL_BASE_UDPHS_FIFO  0x00300000      /* USB Device HS controller */
+#define ATMEL_BASE_OHCI                0x00400000      /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI                0x00500000      /* USB Host controller (EHCI) */
+
+/*
+ * SYSC Spawns
+ */
+#define ATMEL_BASE_RSTC                ATMEL_BASE_SYSC
+#define ATMEL_BASE_SHDWC       (ATMEL_BASE_SYSC + 0x10)
+#define ATMEL_BASE_PIT         (ATMEL_BASE_SYSC + 0x30)
+#define ATMEL_BASE_WDT         (ATMEL_BASE_SYSC + 0x40)
+#define ATMEL_BASE_SCKC                (ATMEL_BASE_SYSC + 0x50)
+#define ATMEL_BASE_RTC         (ATMEL_BASE_SYSC + 0xb0)
+
+/*
+ * Other misc definitions
+ */
+#define ATMEL_BASE_PMECC       (ATMEL_BASE_HSMC + 0x70)
+#define ATMEL_BASE_PMERRLOC    (ATMEL_BASE_HSMC + 0x500)
+
+#define ATMEL_BASE_PIOB                (ATMEL_BASE_PIOA + 0x40)
+#define ATMEL_BASE_PIOC                (ATMEL_BASE_PIOB + 0x40)
+#define ATMEL_BASE_PIOD                (ATMEL_BASE_PIOC + 0x40)
+
+#define ATMEL_PIO_PORTS                4
+#define CPU_HAS_PCR
+#define CPU_HAS_H32MXDIV
+
+/* SAMA5D2 series chip id definitions */
+#define ARCH_ID_SAMA5D2                0x8a5c08c0
+#define ARCH_EXID_SAMA5D21CU   0x0000005a
+#define ARCH_EXID_SAMA5D22CU   0x00000059
+#define ARCH_EXID_SAMA5D22CN   0x00000069
+#define ARCH_EXID_SAMA5D23CU   0x00000058
+#define ARCH_EXID_SAMA5D24CX   0x00000004
+#define ARCH_EXID_SAMA5D24CU   0x00000014
+#define ARCH_EXID_SAMA5D26CU   0x00000012
+#define ARCH_EXID_SAMA5D27CU   0x00000011
+#define ARCH_EXID_SAMA5D27CN   0x00000021
+#define ARCH_EXID_SAMA5D28CU   0x00000010
+#define ARCH_EXID_SAMA5D28CN   0x00000020
+
+#define cpu_is_sama5d2()       (get_chip_id() == ARCH_ID_SAMA5D2)
+
+/* PIT Timer(PIT_PIIR) */
+#define CONFIG_SYS_TIMER_COUNTER       0xf804803c
+
+/* No PMECC Galois table in ROM */
+#define NO_GALOIS_TABLE_IN_ROM
+
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
index 3da8aff27ee6ce154b138aaf935884da737dfa3c..90085da1c6e62970feee38c2a9ff82a5f37bca5d 100644 (file)
 #define CPU_HAS_PCR
 #define CPU_HAS_H32MXDIV
 
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE       0       /* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE      1       /* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_VDEC               2       /* Video Decoder */
+#define H64MX_SLAVE_DDRC_PORT0         3       /* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1         4       /* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2         5       /* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3         6       /* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4         7       /* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5         8       /* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6         9       /* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7         10      /* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM               11      /* Internal SRAM 128K */
+#define H64MX_SLAVE_H32MX_BRIDGE       12      /* Bridge from H64MX to H32MX */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE       0       /* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0     1       /* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1     2       /* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI                        3       /* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD            3       /* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM           4       /* NFC SRAM */
+#define H32MX_SLAVE_USB                        5       /* USB Device & Host */
+#define H32MX_SLAVE_SMD                        6       /* Soft Modem (SMD) */
+
+/* AICREDIR Unlock Key */
+#define ATMEL_SFR_AICREDIR_KEY         0x5F67B102
+
 /* sama5d4 series chip id definitions */
 #define ARCH_ID_SAMA5D4                0x8a5c07c0
 #define ARCH_EXID_SAMA5D41     0x00000001
diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
new file mode 100644 (file)
index 0000000..57d7270
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *                   Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_matrix.h>
+
+void matrix_init(void)
+{
+       struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
+       struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
+       int i;
+
+       /* DDR port 1 ~ port 7 */
+       for (i = H64MX_SLAVE_DDRC_PORT1; i <= H64MX_SLAVE_DDRC_PORT7; i++) {
+               writel(0x000f0f0f, &h64mx->ssr[i]);
+               writel(0x0000ffff, &h64mx->sassr[i]);
+               writel(0x0000000f, &h64mx->srtsr[i]);
+       }
+
+       /* EBI CS3 (NANDFlash 128M) and NFC Command Registers(128M) */
+       writel(0x00c0c0c0, &h32mx->ssr[H32MX_SLAVE_EBI]);
+       writel(0xff000000, &h32mx->sassr[H32MX_SLAVE_EBI]);
+       writel(0xff000000, &h32mx->srtsr[H32MX_SLAVE_EBI]);
+
+       /* NFC SRAM */
+       writel(0x00010101, &h32mx->ssr[H32MX_SLAVE_NFC_SRAM]);
+       writel(0x00000001, &h32mx->sassr[H32MX_SLAVE_NFC_SRAM]);
+       writel(0x00000001, &h32mx->srtsr[H32MX_SLAVE_NFC_SRAM]);
+}
diff --git a/board/atmel/sama5d2_xplained/Kconfig b/board/atmel/sama5d2_xplained/Kconfig
new file mode 100644 (file)
index 0000000..55712e9
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_XPLAINED
+
+config SYS_BOARD
+       default "sama5d2_xplained"
+
+config SYS_VENDOR
+       default "atmel"
+
+config SYS_SOC
+       default "at91"
+
+config SYS_CONFIG_NAME
+       default "sama5d2_xplained"
+
+endif
diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS
new file mode 100644 (file)
index 0000000..ff9c86f
--- /dev/null
@@ -0,0 +1,7 @@
+SAMA5D2 XPLAINED BOARD
+M:     Wenyou Yang <wenyou.yang@atmel.com>
+S:     Maintained
+F:     board/atmel/sama5d2_xplained/
+F:     include/configs/sama5d2_xplained.h
+F:     configs/sama5d2_xplained_mmc_defconfig
+F:     configs/sama5d2_xplained_spiflash_defconfig
diff --git a/board/atmel/sama5d2_xplained/Makefile b/board/atmel/sama5d2_xplained/Makefile
new file mode 100644 (file)
index 0000000..420870b
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2015 Atmel Corporation
+#                   Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += sama5d2_xplained.o
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
new file mode 100644 (file)
index 0000000..0b3397f
--- /dev/null
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *                   Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+       atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+       at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_usb_hw_init(void)
+{
+       atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
+}
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+       .vl_col = 480,
+       .vl_row = 272,
+       .vl_clk = 9000000,
+       .vl_bpix = LCD_BPP,
+       .vl_tft = 1,
+       .vl_hsync_len = 41,
+       .vl_left_margin = 2,
+       .vl_right_margin = 2,
+       .vl_vsync_len = 11,
+       .vl_upper_margin = 2,
+       .vl_lower_margin = 2,
+       .mmio = ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void)  { /* Empty! */ }
+void lcd_disable(void) { /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+       return 1;
+}
+
+static void board_lcd_hw_init(void)
+{
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTD,  0, 0); /* LCDPCK */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTD,  1, 0); /* LCDDEN */
+
+       /* LCDDAT0 */
+       /* LCDDAT1 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
+
+       /* LCDDAT8 */
+       /* LCDDAT9 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
+
+       /* LCDD16 */
+       /* LCDD17 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
+
+       at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+       ulong dram_size;
+       int i;
+       char temp[32];
+
+       lcd_printf("%s\n", U_BOOT_VERSION);
+       lcd_printf("2015 ATMEL Corp\n");
+       lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+                  strmhz(temp, get_cpu_clk_rate()));
+
+       dram_size = 0;
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+               dram_size += gd->bd->bi_dram[i].size;
+
+       lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+static void board_gmac_hw_init(void)
+{
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
+
+       at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_sdhci0_hw_init(void)
+{
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);  /* SDMMC0_CK */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);  /* SDMMC0_CMD */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);  /* SDMMC0_DAT0 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);  /* SDMMC0_DAT1 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);  /* SDMMC0_DAT2 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);  /* SDMMC0_DAT3 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0);  /* SDMMC0_DAT4 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0);  /* SDMMC0_DAT5 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0);  /* SDMMC0_DAT6 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0);  /* SDMMC0_DAT7 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */
+
+       at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+       at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
+                                        GCK_CSS_PLLA_CLK, 1);
+}
+
+static void board_sdhci1_hw_init(void)
+{
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */
+       atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */
+
+       at91_periph_clk_enable(ATMEL_ID_SDMMC1);
+       at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
+                                        GCK_CSS_PLLA_CLK, 1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_ATMEL_SDHCI0
+       atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0);
+#endif
+#ifdef CONFIG_ATMEL_SDHCI1
+       atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1);
+#endif
+
+       return 0;
+}
+
+static void board_uart1_hw_init(void)
+{
+       atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1);  /* URXD1 */
+       atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);  /* UTXD1 */
+
+       at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+int board_early_init_f(void)
+{
+       at91_periph_clk_enable(ATMEL_ID_PIOA);
+       at91_periph_clk_enable(ATMEL_ID_PIOB);
+       at91_periph_clk_enable(ATMEL_ID_PIOC);
+       at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+       board_uart1_hw_init();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+       board_spi0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI
+#ifdef CONFIG_ATMEL_SDHCI0
+       board_sdhci0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI1
+       board_sdhci1_hw_init();
+#endif
+#endif
+#ifdef CONFIG_MACB
+       board_gmac_hw_init();
+#endif
+#ifdef CONFIG_LCD
+       board_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+       board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       at91_udp_hw_init();
+#endif
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+
+#ifdef CONFIG_MACB
+       rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+       usb_eth_initialize(bis);
+#endif
+#endif
+
+       return rc;
+}
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
new file mode 100644 (file)
index 0000000..c1dcbef
--- /dev/null
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
new file mode 100644 (file)
index 0000000..0271e8e
--- /dev/null
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
index 9e494713fbcc9648dece7bf0f3e9ab29af9cb3ca..e60e9fd86c39a0068689079448555aea3deb4ff9 100644 (file)
@@ -28,6 +28,17 @@ config DWAPB_GPIO
        help
          Support for the Designware APB GPIO driver.
 
+config ATMEL_PIO4
+       bool "ATMEL PIO4 driver"
+       depends on DM
+       default n
+       help
+         Say yes here to support the Atmel PIO4 driver.
+         The PIO4 is new version of Atmel PIO controller, which manages
+         up to 128 fully programmable input/output lines. Each I/O line
+         may be dedicated as a general purpose I/O or be assigned to
+         a function of an embedded peripheral.
+
 config LPC32XX_GPIO
        bool "LPC32XX GPIO driver"
        depends on DM
index c58aa4dfd5aa2d8f447e5946d55f431480a5de45..fb4fd255df334672cfe0086a0a447e75fc06e029 100644 (file)
@@ -12,6 +12,7 @@ endif
 obj-$(CONFIG_DM_GPIO)          += gpio-uclass.o
 
 obj-$(CONFIG_AT91_GPIO)        += at91_gpio.o
+obj-$(CONFIG_ATMEL_PIO4)       += atmel_pio4.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)  += intel_ich6_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)    += kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)        += kona_gpio.o
diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c
new file mode 100644 (file)
index 0000000..d71f525
--- /dev/null
@@ -0,0 +1,296 @@
+/*
+ * Atmel PIO4 device driver
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ *              Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/hardware.h>
+#include <mach/gpio.h>
+#include <mach/atmel_pio4.h>
+
+#define ATMEL_PIO4_PINS_PER_BANK       32
+
+/*
+ * Register Field Definitions
+ */
+#define ATMEL_PIO4_CFGR_FUNC   (0x7 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_GPIO       (0x0 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_PERIPH_A   (0x1 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_PERIPH_B   (0x2 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_PERIPH_C   (0x3 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_PERIPH_D   (0x4 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_PERIPH_E   (0x5 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_PERIPH_F   (0x6 << 0)
+#define                ATMEL_PIO4_CFGR_FUNC_PERIPH_G   (0x7 << 0)
+#define ATMEL_PIO4_CFGR_DIR    (0x1 << 8)
+#define ATMEL_PIO4_CFGR_PUEN   (0x1 << 9)
+#define ATMEL_PIO4_CFGR_PDEN   (0x1 << 10)
+#define ATMEL_PIO4_CFGR_IFEN   (0x1 << 12)
+#define ATMEL_PIO4_CFGR_IFSCEN (0x1 << 13)
+#define ATMEL_PIO4_CFGR_OPD    (0x1 << 14)
+#define ATMEL_PIO4_CFGR_SCHMITT        (0x1 << 15)
+#define ATMEL_PIO4_CFGR_DRVSTR (0x3 << 16)
+#define                ATMEL_PIO4_CFGR_DRVSTR_LOW0     (0x0 << 16)
+#define                ATMEL_PIO4_CFGR_DRVSTR_LOW1     (0x1 << 16)
+#define                ATMEL_PIO4_CFGR_DRVSTR_MEDIUM   (0x2 << 16)
+#define                ATMEL_PIO4_CFGR_DRVSTR_HIGH     (0x3 << 16)
+#define ATMEL_PIO4_CFGR_EVTSEL (0x7 << 24)
+#define                ATMEL_PIO4_CFGR_EVTSEL_FALLING  (0x0 << 24)
+#define                ATMEL_PIO4_CFGR_EVTSEL_RISING   (0x1 << 24)
+#define                ATMEL_PIO4_CFGR_EVTSEL_BOTH     (0x2 << 24)
+#define                ATMEL_PIO4_CFGR_EVTSEL_LOW      (0x3 << 24)
+#define                ATMEL_PIO4_CFGR_EVTSEL_HIGH     (0x4 << 24)
+#define ATMEL_PIO4_CFGR_PCFS   (0x1 << 29)
+#define ATMEL_PIO4_CFGR_ICFS   (0x1 << 30)
+
+static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
+{
+       struct atmel_pio4_port *base = NULL;
+
+       switch (port) {
+       case AT91_PIO_PORTA:
+               base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
+               break;
+       case AT91_PIO_PORTB:
+               base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
+               break;
+       case AT91_PIO_PORTC:
+               base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
+               break;
+       case AT91_PIO_PORTD:
+               base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
+               break;
+       default:
+               printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
+                      port);
+               break;
+       }
+
+       return base;
+}
+
+static int atmel_pio4_config_io_func(u32 port, u32 pin,
+                                    u32 func, u32 use_pullup)
+{
+       struct atmel_pio4_port *port_base;
+       u32 reg, mask;
+
+       if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+               return -ENODEV;
+
+       port_base = atmel_pio4_port_base(port);
+       if (!port_base)
+               return -ENODEV;
+
+       mask = 1 << pin;
+       reg = func;
+       reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0;
+
+       writel(mask, &port_base->mskr);
+       writel(reg, &port_base->cfgr);
+
+       return 0;
+}
+
+int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_GPIO,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_PERIPH_A,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_PERIPH_B,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_PERIPH_C,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_PERIPH_D,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_PERIPH_E,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_PERIPH_F,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup)
+{
+       return atmel_pio4_config_io_func(port, pin,
+                                        ATMEL_PIO4_CFGR_FUNC_PERIPH_G,
+                                        use_pullup);
+}
+
+int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
+{
+       struct atmel_pio4_port *port_base;
+       u32 reg, mask;
+
+       if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+               return -ENODEV;
+
+       port_base = atmel_pio4_port_base(port);
+       if (!port_base)
+               return -ENODEV;
+
+       mask = 0x01 << pin;
+       reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
+
+       writel(mask, &port_base->mskr);
+       writel(reg, &port_base->cfgr);
+
+       if (value)
+               writel(mask, &port_base->sodr);
+       else
+               writel(mask, &port_base->codr);
+
+       return 0;
+}
+
+int atmel_pio4_get_pio_input(u32 port, u32 pin)
+{
+       struct atmel_pio4_port *port_base;
+       u32 reg, mask;
+
+       if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+               return -ENODEV;
+
+       port_base = atmel_pio4_port_base(port);
+       if (!port_base)
+               return -ENODEV;
+
+       mask = 0x01 << pin;
+       reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
+
+       writel(mask, &port_base->mskr);
+       writel(reg, &port_base->cfgr);
+
+       return (readl(&port_base->pdsr) & mask) ? 1 : 0;
+}
+
+#ifdef CONFIG_DM_GPIO
+static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
+{
+       struct at91_port_platdata *plat = dev_get_platdata(dev);
+       struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+       u32 mask = 0x01 << offset;
+       u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
+
+       writel(mask, &port_base->mskr);
+       writel(reg, &port_base->cfgr);
+
+       return 0;
+}
+
+static int atmel_pio4_direction_output(struct udevice *dev,
+                                      unsigned offset, int value)
+{
+       struct at91_port_platdata *plat = dev_get_platdata(dev);
+       struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+       u32 mask = 0x01 << offset;
+       u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
+
+       writel(mask, &port_base->mskr);
+       writel(reg, &port_base->cfgr);
+
+       if (value)
+               writel(mask, &port_base->sodr);
+       else
+               writel(mask, &port_base->codr);
+
+       return 0;
+}
+
+static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
+{
+       struct at91_port_platdata *plat = dev_get_platdata(dev);
+       struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+       u32 mask = 0x01 << offset;
+
+       return (readl(&port_base->pdsr) & mask) ? 1 : 0;
+}
+
+static int atmel_pio4_set_value(struct udevice *dev,
+                               unsigned offset, int value)
+{
+       struct at91_port_platdata *plat = dev_get_platdata(dev);
+       struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+       u32 mask = 0x01 << offset;
+
+       if (value)
+               writel(mask, &port_base->sodr);
+       else
+               writel(mask, &port_base->codr);
+
+       return 0;
+}
+
+static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
+{
+       struct at91_port_platdata *plat = dev_get_platdata(dev);
+       struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+       u32 mask = 0x01 << offset;
+
+       writel(mask, &port_base->mskr);
+
+       return (readl(&port_base->cfgr) &
+               ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops atmel_pio4_ops = {
+       .direction_input        = atmel_pio4_direction_input,
+       .direction_output       = atmel_pio4_direction_output,
+       .get_value              = atmel_pio4_get_value,
+       .set_value              = atmel_pio4_set_value,
+       .get_function           = atmel_pio4_get_function,
+};
+
+static int atmel_pio4_probe(struct udevice *dev)
+{
+       struct at91_port_platdata *plat = dev_get_platdata(dev);
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+       uc_priv->bank_name = plat->bank_name;
+       uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK;
+
+       return 0;
+}
+
+U_BOOT_DRIVER(gpio_atmel_pio4) = {
+       .name   = "gpio_atmel_pio4",
+       .id     = UCLASS_GPIO,
+       .ops    = &atmel_pio4_ops,
+       .probe  = atmel_pio4_probe,
+};
+#endif
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
new file mode 100644 (file)
index 0000000..ae5ba3d
--- /dev/null
@@ -0,0 +1,122 @@
+/*
+ * Configuration file for the SAMA5D2 Xplained Board.
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ *                   Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE              ATMEL_BASE_UART1
+#define CONFIG_USART_ID                        ATMEL_ID_UART1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE          0x20000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LOAD_ADDR           0x22000000 /* load address */
+
+#undef CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_PIO4
+
+/* SerialFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_ATMEL_SPI0
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS          0
+#define CONFIG_SF_DEFAULT_CS           0
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#endif
+
+/* NAND flash */
+#undef CONFIG_CMD_NAND
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_ATMEL_SDHCI
+#define CONFIG_ATMEL_SDHCI0
+#define CONFIG_ATMEL_SDHCI1
+#define CONFIG_SUPPORT_EMMC_BOOT
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS     3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D2 XPlained"
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT         20
+#define CONFIG_MACB_SEARCH_PHY
+
+/* LCD */
+/* #define CONFIG_LCD */
+
+#ifdef CONFIG_LCD
+#define LCD_BPP                                LCD_COLOR16
+#define LCD_OUTPUT_BPP                  24
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+
+/* bootstrap + u-boot + env in sd card */
+#undef FAT_ENV_DEVICE_AND_PART
+#undef CONFIG_BOOTCOMMAND
+
+#define FAT_ENV_DEVICE_AND_PART        "1"
+#define CONFIG_BOOTCOMMAND     "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \
+                               "fatload mmc 1:1 0x22000000 zImage; " \
+                               "bootz 0x22000000 - 0x21000000"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+       "console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
+
+#endif
+
+#endif