S: Maintained
T: git git://git.denx.de/u-boot-samsung.git
F: arch/arm/cpu/arm920t/s3c24x0/
-F: arch/arm/cpu/armv7/exynos/
-F: arch/arm/cpu/armv7/s5pc1xx/
+F: arch/arm/mach-exynos/
+F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
-F: arch/arm/include/asm/arch-exynos/
F: arch/arm/include/asm/arch-s3c24x0/
-F: arch/arm/include/asm/arch-s5pc1xx/
ARM STM SPEAR
M: Vipin Kumar <vipin.kumar@st.com>
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
+ CONFIG_SYS_FSL_HAS_DP_DDR
+ Defines the SoC has DP-DDR used for DPAA.
+
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian
bool "Support Versatile Express Juno Development Platform"
select ARM64
-config TARGET_LS2085A_EMU
- bool "Support ls2085a_emu"
+config TARGET_LS2080A_EMU
+ bool "Support ls2080a_emu"
select ARM64
select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2080A_EMU platform
+ The LS2080A Development System (EMULATOR) is a pre silicon
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_LS2085A_SIMU
- bool "Support ls2085a_simu"
+config TARGET_LS2080A_SIMU
+ bool "Support ls2080a_simu"
select ARM64
select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2080A_SIMU platform
+ The LS2080A Development System (QDS) is a pre silicon
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_LS2085AQDS
- bool "Support ls2085aqds"
+config TARGET_LS2080AQDS
+ bool "Support ls2080aqds"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
- Support for Freescale LS2085AQDS platform
- The LS2085A Development System (QDS) is a high-performance
- development platform that supports the QorIQ LS2085A
+ Support for Freescale LS2080AQDS platform
+ The LS2080A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
-config TARGET_LS2085ARDB
- bool "Support ls2085ardb"
+config TARGET_LS2080ARDB
+ bool "Support ls2080ardb"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
- Support for Freescale LS2085ARDB platform.
- The LS2085A Reference design board (RDB) is a high-performance
- development platform that supports the QorIQ LS2085A
+ Support for Freescale LS2080ARDB platform.
+ The LS2080A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_HIKEY
select CPU_V7
select SUPPORT_SPL
+config TARGET_LS1043AQDS
+ bool "Support ls1043aqds"
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
+ help
+ Support for Freescale LS1043AQDS platform.
+
config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARM64
source "arch/arm/mach-rockchip/Kconfig"
-source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
+source "arch/arm/mach-s5pc1xx/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
-source "board/freescale/ls2085a/Kconfig"
-source "board/freescale/ls2085aqds/Kconfig"
-source "board/freescale/ls2085ardb/Kconfig"
+source "board/freescale/ls2080a/Kconfig"
+source "board/freescale/ls2080aqds/Kconfig"
+source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
+source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/mx23evk/Kconfig"
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
+machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_TEGRA) += tegra
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_RMOBILE) += rmobile/
-obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/
*/
}
}
+
+void arch_preboot_os(void)
+{
+ unsigned long ctrl;
+
+ /* Disable PL1 Physical Timer */
+ asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
+ ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+ asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+}
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
- unsigned long ctrl, val, freq;
+ unsigned long ctrl, freq;
+ unsigned long long val;
/* Enable System Counter */
writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
#ifndef CONFIG_SYS_DCACHE_OFF
inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
- u64 memory_type, u64 share)
+ u64 memory_type, u64 attribute)
{
u64 value;
value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
- value |= share;
+ value |= attribute;
page_table[index] = value;
}
endif
endif
+ifneq ($(CONFIG_LS2080A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
+endif
+
ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
-else
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
+endif
+
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
endif
-endif
Freescale LayerScape with Chassis Generation 3
This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
-for example LS2085A.
+for example LS2080A.
DDR Layout
============
nand write <rcw image in memory> 0 <size of rcw image>
To form the NAND image, build u-boot with NAND config, for example,
-ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
nand write <u-boot image in memory> 200000 <size of u-boot image>
| 0x81_0000_0000 | | 0x08_0080_0000 |
------------------ ------------------
... ...
+
+
+DPAA2 commands to manage Management Complex (MC)
+------------------------------------------------
+DPAA2 commands has been introduced to manage Management Complex
+(MC). These commands are used to start mc, aiop and apply DPL
+from u-boot command prompt.
+
+Please note Management complex Firmware(MC), DPL and DPC are no
+more deployed during u-boot boot-sequence.
+
+Commands:
+a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+c) fsl_mc start aiop <FW_addr> - Start AIOP
+
+How to use commands :-
+1. Command sequence for u-boot ethernet:
+ a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+ b) DPMAC net-devices are now available for use
+
+ Example-
+ Assumption: MC firmware, DPL and DPC dtb is already programmed
+ on NOR flash.
+
+ => fsl_mc start mc 580300000 580800000
+ => setenv ethact DPMAC1@xgmii
+ => ping $serverip
+
+2. Command sequence for Linux boot:
+ a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+ b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+ c) No DPMAC net-devices are available for use in u-boot
+ d) boot Linux
+
+ Example-
+ Assumption: MC firmware, DPL and DPC dtb is already programmed
+ on NOR flash.
+
+ => fsl_mc start mc 580300000 580800000
+ => setenv ethact DPMAC1@xgmii
+ => tftp a0000000 kernel.itb
+ => fsl_mc apply dpl 580700000
+ => bootm a0000000
+
+3. Command sequence for AIOP boot:
+ a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+ b) fsl_mc start aiop <FW_addr> - Start AIOP
+ c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+ d) No DPMAC net-devices are availabe for use in u-boot
+ Please note actual AIOP start will happen during DPL parsing of
+ Management complex
+
+ Example-
+ Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
+ programmed on NOR flash.
+
+ => fsl_mc start mc 580300000 580800000
+ => fsl_mc start aiop 0x580900000
+ => setenv ethact DPMAC1@xgmii
+ => fsl_mc apply dpl 580700000
+
+Errata A009635
+---------------
+If the core runs at higher than x3 speed of the platform, there is
+possiblity about sev instruction to getting missed by other cores.
+This is because of SoC Run Control block may not able to sample
+the EVENTI(Sev) signals.
+
+Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
+wake up A57 cores
+
+Errata workaround uses Env variable "a009635_interval_val". It uses decimal
+value.
+- Default value of env variable is platform clock (MHz)
+
+- User can modify default value by updating the env variable
+ setenv a009635_interval_val 600; saveenv;
+ It configure platform clock as 600 MHz
+
+- Env variable as 0 signifies no workaround
index,
block_addr,
list->memory_type,
- list->share);
+ list->attribute);
block_addr += block_size;
index++;
}
#ifdef CONFIG_SYS_DPAA_FMAN
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
#endif
puts("\n");
{
#ifdef CONFIG_MP
int rv = 1;
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+ erratum_a009635();
+#endif
+
+#ifdef CONFIG_MP
rv = fsl_layerscape_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
/*
* The info below summarizes how streamID partitioning works
- * for ls2085a and how it is conveyed to the OS via the device tree.
+ * for ls2080a and how it is conveyed to the OS via the device tree.
*
* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
* -all legacy devices get a unique ICID assigned and programmed in
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
+#ifdef CONFIG_FSL_MC_ENET
+int xfi_dpmac[XFI8 + 1];
+int sgmii_dpmac[SGMII16 + 1];
+#endif
+
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
wriop_init_dpmac(sd, 12, (int)lane_prtcl);
break;
default:
+ if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
+ wriop_init_dpmac(sd,
+ xfi_dpmac[lane_prtcl],
+ (int)lane_prtcl);
+
if (lane_prtcl >= SGMII1 &&
- lane_prtcl <= SGMII16)
- wriop_init_dpmac(sd, lane + 1,
+ lane_prtcl <= SGMII16)
+ wriop_init_dpmac(sd, sgmii_dpmac[
+ lane_prtcl],
(int)lane_prtcl);
break;
}
void fsl_serdes_init(void)
{
+#ifdef CONFIG_FSL_MC_ENET
+ int i , j;
+
+ for (i = XFI1, j = 1; i <= XFI8; i++, j++)
+ xfi_dpmac[i] = j;
+
+ for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
+ sgmii_dpmac[i] = j;
+#endif
+
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include "cpu.h"
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
+#endif
#else
sys_info->freq_ddrbus = sysclk;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 = sysclk;
+#endif
#endif
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+#endif
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
+#endif
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
* DDR controller 0 & 1 are on memory complex 0
* DDR controler 2 is on memory complext 1
*/
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num >= 2)
return gd->arch.mem2_clk;
+#endif
return gd->mem_clk;
}
SGMII1 } },
{0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
{0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+#ifdef CONFIG_LS2080A
+ {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+#endif
+#ifdef CONFIG_LS2085A
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+#endif
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
smp_kick_all_cpus(); /* only those with entry addr set will run */
+ /*
+ * When the first release command runs, all cores are set to go. Those
+ * without a valid entry address will be trapped by "wfe". "sev" kicks
+ * them off to check the address again. When set, they continue to run.
+ */
+ asm volatile("sev");
return 0;
}
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
+#include <asm/arch-fsl-layerscape/config.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
+
+static unsigned long get_internval_val_mhz(void)
+{
+ char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
+ /*
+ * interval is the number of platform cycles(MHz) between
+ * wake up events generated by EPU.
+ */
+ ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
+
+ if (interval)
+ interval_mhz = simple_strtoul(interval, NULL, 10);
+
+ return interval_mhz;
+}
+
+void erratum_a009635(void)
+{
+ u32 val;
+ unsigned long interval_mhz = get_internval_val_mhz();
+
+ if (!interval_mhz)
+ return;
+
+ val = in_le32(DCSR_CGACRE5);
+ writel(val | 0x00000200, DCSR_CGACRE5);
+
+ val = in_le32(EPU_EPCMPR5);
+ writel(interval_mhz, EPU_EPCMPR5);
+ val = in_le32(EPU_EPCCR5);
+ writel(val | 0x82820000, EPU_EPCCR5);
+ val = in_le32(EPU_EPSMCR5);
+ writel(val | 0x002f0000, EPU_EPSMCR5);
+ val = in_le32(EPU_EPECR5);
+ writel(val | 0x20000000, EPU_EPECR5);
+ val = in_le32(EPU_EPGCR);
+ writel(val | 0x80000000, EPU_EPGCR);
+}
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
+
static void erratum_a008751(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- /* Set global data pointer */
- gd = &gdata;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
#endif
board_early_init_f();
timer_init();
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
env_init();
#endif
get_clocks();
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr.dtb
-dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
- fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ fsl-ls2080a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+ fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
--- /dev/null
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+ model = "LS1043A QDS Board";
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "philips,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ /* IRQ10_B */
+ interrupts = <0 150 0x4>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a@4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ status = "okay";
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ fpga: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ reg = <0x3 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 3 0 0x100>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+ model = "LS1043A RDB Board";
+
+ aliases {
+ spi1 = &dspi0;
+ };
+
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: n25q12a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
+
+};
+
+&i2c0 {
+ status = "okay";
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ adt7461a@4c {
+ compatible = "adi,adt7461a";
+ reg = <0x4c>;
+ };
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x52>;
+ };
+
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x53>;
+ };
+
+ rtc@68 {
+ compatible = "pericom,pt7c4338";
+ reg = <0x68>;
+ };
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@1,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ cpld: board-control@2,0 {
+ compatible = "fsl,ls1043ardb-cpld";
+ reg = <0x2 0x0 0x0000100>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+ compatible = "fsl,ls1043a";
+ interrupt-parent = <&gic>;
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&clockgen 1 0>;
+ };
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x2000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1043a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <0 43 0x4>;
+ };
+
+ i2c0: i2c@2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <0 58 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <0 59 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart2: serial@21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart3: serial@21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+ };
+};
/*
- * Freescale ls2085a QDS board device tree source
+ * Freescale ls2080a QDS board device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
/dts-v1/;
-#include "fsl-ls2085a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
- model = "Freescale Layerscape 2085a QDS Board";
- compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
+ model = "Freescale Layerscape 2080a QDS Board";
+ compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
aliases {
spi1 = &dspi;
/*
- * Freescale ls2085a RDB board device tree source
+ * Freescale ls2080a RDB board device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
/dts-v1/;
-#include "fsl-ls2085a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
- model = "Freescale Layerscape 2085a RDB Board";
- compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
+ model = "Freescale Layerscape 2080a RDB Board";
+ compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
aliases {
spi1 = &dspi;
/*
- * Freescale ls2085a SOC common device tree source
+ * Freescale ls2080a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
*/
/ {
- compatible = "fsl,ls2085a";
+ compatible = "fsl,ls2080a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ drvsel = <3>;
+ smplsel = <0>;
};
sysmgr@ffd08000 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ drvsel = <3>;
+ smplsel = <0>;
};
sysmgr@ffd08000 {
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
};
&gmac1 {
&mmc0 {
status = "okay";
+ u-boot,dm-pre-reloc;
};
&qspi {
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#ifdef CONFIG_LS2080A
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#endif
+#ifdef CONFIG_LS2085A
#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_SYS_FSL_HAS_DP_DDR
+#endif
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
#define CONFIG_SYS_FSL_ESDHC_LE
#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
+#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
+#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
+#define CCN_HN_F_SAM_NODEID_MASK 0x7f
+#define CCN_HN_F_SAM_NODEID_DDR0 0x4
+#define CCN_HN_F_SAM_NODEID_DDR1 0xe
+
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+#define DCSR_CGACRE5 0x700070914ULL
+#define EPU_EPCMPR5 0x700060914ULL
+#define EPU_EPCCR5 0x700060814ULL
+#define EPU_EPSMCR5 0x700060228ULL
+#define EPU_EPECR5 0x700060314ULL
+#define EPU_EPCTR5 0x700060a14ULL
+#define EPU_EPGCR 0x700060000ULL
+
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009635
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define _FSL_LAYERSCAPE_CPU_H
static struct cpu_type cpu_type_list[] = {
- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+ CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
};
u64 phys_addr;
u64 size;
u64 memory_type;
- u64 share;
+ u64 attribute;
};
struct table_info {
static const struct sys_mmu_table early_mmu_table[] = {
#ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
/* For IFC Region #1, only the first 4MB is cache-enabled */
CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
static const struct sys_mmu_table final_mmu_table[] = {
#ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
- CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
- CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
- CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
/* For QBMAN portal, only the first 64MB is cache-enabled */
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
- MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
- CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
- CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
- CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
- CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
- CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#endif
void append_mmu_masters(void *blob, const char *smmu_path,
const char *master_name, u32 *stream_ids, int count);
void fdt_fixup_smmu_pcie(void *blob);
+void fdt_fixup_board_enet(void *fdt);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
#include <config.h>
-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
enum srds_prtcl {
NONE = 0,
PCIE1,
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
+/* LUT registers */
+#define PCIE_LUT_BASE 0x10000
+#define PCIE_LUT_LCTRL0 0x7F8
+#define PCIE_LUT_DBG 0x7FC
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
-#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+/* LUT registers */
+#define PCIE_LUT_BASE 0x80000
+#define PCIE_LUT_LCTRL0 0x7F8
+#define PCIE_LUT_DBG 0x7FC
/* Device Configuration */
#define DCFG_BASE 0x01e00000
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
unsigned long freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
unsigned long freq_ddrbus2;
+#endif
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef __FSL_STREAM_ID_H
#define __FSL_STREAM_ID_H
-/* Stream IDs on ls2085a devices are not hardwired and are
+/* Stream IDs on ls2080a devices are not hardwired and are
* programmed by sw. There are a limited number of stream IDs
* available, and the partitioning of them is scenario dependent.
* This header defines the partitioning between legacy, PCI,
* on the specific hardware config-- e.g. perhaps not all
* PEX controllers are in use.
*
- * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
+ * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
* each of the different bus masters. The relationship between
* the AMQ registers and stream IDs is defined in the table below:
* AMQ bit streamID bit
#define scfg_out32(a, v) out_be32(a, v)
#endif
+#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
+#define pex_lut_in32(a) in_le32(a)
+#define pex_lut_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
+#define pex_lut_in32(a) in_be32(a)
+#define pex_lut_out32(a, v) out_be32(a, v)
+#endif
+
struct cpu_type {
char name[15];
u32 soc_ver;
#endif
void cpu_name(char *name);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+void erratum_a009635(void);
+#endif
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
#define RCWSR4_SRDS1_PRTCL_SHIFT 24
#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
-#define TIMER_COMP_VAL 0xffffffff
+#define TIMER_COMP_VAL 0xffffffffffffffffull
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
void set_pgtable_section(u64 *page_table, u64 index,
u64 section, u64 memory_type,
- u64 share);
+ u64 attribute);
void set_pgtable_table(u64 *page_table, u64 index,
u64 *table_addr);
u32 omap_boot_mode;
u8 omap_ch_flags;
#endif
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
unsigned long mem2_clk;
#endif
};
config TARGET_NAS220
bool "BlackArmor NAS220"
+config TARGET_NSA310S
+ bool "Zyxel NSA310S"
+
endchoice
config SYS_SOC
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
+source "board/zyxel/nsa310s/Kconfig"
endif
#define CONFIG_PHYLIB
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
#endif /* CONFIG_CMD_NET */
/*
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_EBV_SOCRATES
+ bool "EBV SoCrates (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+ default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
endif
--- /dev/null
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
+#define _SOCFPGA_A10_BASE_HARDWARE_H_
+
+#define SOCFPGA_EMAC0_ADDRESS 0xff800000
+#define SOCFPGA_EMAC1_ADDRESS 0xff802000
+#define SOCFPGA_EMAC2_ADDRESS 0xff804000
+#define SOCFPGA_SDMMC_ADDRESS 0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000
+#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
+#define SOCFPGA_UART1_ADDRESS 0xffc02100
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400
+#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000
+#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200
+#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300
+#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400
+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
+#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000
+#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
+#define SOCFPGA_I2C0_ADDRESS 0xffc02200
+#define SOCFPGA_I2C1_ADDRESS 0xffc02300
+
+#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#define SOCFPGA_SDR_ADDRESS 0xffcfb000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
+#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
+
+#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
u32 per2_mod_reset;
u32 brg_mod_reset;
u32 misc_mod_reset;
+ u32 padding2[12];
u32 tstscratch;
};
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/lwmon5/Kconfig"
+source "board/liebherr/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
..no_pllset:
#endif /* CONFIG_BUBINGA */
-#ifdef CONFIG_TAIHU
- mfdcr r4, CPC0_BOOT
- andi. r5, r4, CPC0_BOOT_SEP@l
- bne strap_1 /* serial eeprom present */
- addis r5,0,CPLD_REG0_ADDR@h
- ori r5,r5,CPLD_REG0_ADDR@l
- andi. r5, r5, 0x10
- bne _pci_66mhz
-#endif /* CONFIG_TAIHU */
-
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
ori r4,r4,PLLMR1_DEFAULT@l /* */
-#ifdef CONFIG_TAIHU
- b 1f
-_pci_66mhz:
- addis r3,0,PLLMR0_DEFAULT_PCI66@h
- ori r3,r3,PLLMR0_DEFAULT_PCI66@l
- addis r4,0,PLLMR1_DEFAULT_PCI66@h
- ori r4,r4,PLLMR1_DEFAULT_PCI66@l
- b 1f
-strap_1:
- mfdcr r3, CPC0_PLLMR0
- mfdcr r4, CPC0_PLLMR1
-#endif /* CONFIG_TAIHU */
-
1:
b pll_write /* Write the CPC0_PLLMR with new value */
--- /dev/null
+SOCRATES BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/ebv/socrates/
+F: include/configs/socfpga_socrates.h
+F: configs/socfpga_socrates_defconfig
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
--- /dev/null
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00004824,
+ 0x01209000,
+ 0x82400000,
+ 0x00018004,
+ 0x00000000,
+ 0x00004000,
+ 0x00002412,
+ 0x00904800,
+ 0x41200000,
+ 0x80000002,
+ 0x00000904,
+ 0x00002000,
+ 0x00001209,
+ 0x00482400,
+ 0x20900000,
+ 0x40000001,
+ 0x00000482,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00009048,
+ 0x02412000,
+ 0x048000C0,
+ 0x00000009,
+ 0x00002412,
+ 0x00008000,
+ 0x00004824,
+ 0x01209000,
+ 0x82400000,
+ 0x00000004,
+ 0x00001209,
+ 0x00004000,
+ 0x00002412,
+ 0x00904800,
+ 0x41200000,
+ 0x80000002,
+ 0x00000904,
+ 0x00002000,
+ 0x06001209,
+ 0x00482400,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x80001000,
+ 0x00000904,
+ 0x00241200,
+ 0x90480000,
+ 0x20003000,
+ 0x00000241,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x48240000,
+ 0x90000000,
+ 0x00000120,
+ 0x00000400,
+ 0x00000000,
+ 0x00090480,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x90000200,
+ 0x00600120,
+ 0x00000000,
+ 0x12090000,
+ 0x24000600,
+ 0x00000048,
+ 0x48000100,
+ 0x00300090,
+ 0xC0024120,
+ 0x09048000,
+ 0x12000300,
+ 0x000C0024,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x30009048,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C002412,
+ 0x00008000,
+ 0x18004824,
+ 0x00000000,
+ 0x82400000,
+ 0x00018004,
+ 0x06001209,
+ 0x00004000,
+ 0x20002412,
+ 0x00904800,
+ 0x00000030,
+ 0x80000000,
+ 0x03000904,
+ 0x00002000,
+ 0x10001209,
+ 0x00482400,
+ 0x20900000,
+ 0x40010001,
+ 0x00000482,
+ 0x80001000,
+ 0x00000904,
+ 0x00000000,
+ 0x90480000,
+ 0x20008000,
+ 0x00C00241,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0CC20D80,
+ 0x0C3000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x45034030,
+ 0x12481A01,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A01450,
+ 0x280D0000,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD000001A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000FF0,
+ 0x4810C000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x24086001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x49034030,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A00040,
+ 0x280D0002,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD00A281A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF228A3D5,
+ 0xF6D1451E,
+ 0x0342E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x05140680,
+ 0xD949247A,
+ 0x1EF228A3,
+ 0x88F6D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x86120800,
+ 0x00600240,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF3CF23D5,
+ 0xF4D1451E,
+ 0x034A9248,
+ 0x821A038E,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF3CF23,
+ 0x88F4D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF228A3D9,
+ 0xF4D1451E,
+ 0x034A9248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF228A3,
+ 0x88F4D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x08864000,
+ 0x49247A02,
+ 0xF3CF23D9,
+ 0xF4D1451E,
+ 0x0342E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF3CF23,
+ 0x88F4DE79,
+ 0x000342A2,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 375
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 82
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 82
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080221,
+ 0x10080320,
+ 0x10090044,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080241,
+ 0x100802c0,
+ 0x100a0024,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+#include <micrel.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
#include <common.h>
#include <command.h>
#include <i2c.h>
+#include <asm/io.h>
+#ifdef CONFIG_LS1043A
+#include <asm/arch/immap_lsch2.h>
+#else
#include <asm/immap_85xx.h>
+#endif
#include "vid.h"
DECLARE_GLOBAL_DATA_PTR;
* SoC before converting into an IR VID value
*/
vdd += board_vdd_drop_compensation();
+#ifdef CONFIG_LS1043A
+ vid = DIV_ROUND_UP(vdd - 265, 5);
+#else
vid = DIV_ROUND_UP(vdd - 245, 5);
+#endif
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
+#ifdef CONFIG_LS1043A
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#else
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
u32 fusesr;
u8 vid;
int vdd_target, vdd_current, vdd_last;
* | T | | | | |
* ------------------------------------------------------
*/
+#ifdef CONFIG_LS1043A
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
+ }
+#else
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_VID_MASK;
}
+#endif
vdd_target = vdd[vid];
/* check override variable for overriding VDD */
--- /dev/null
+if TARGET_LS1043AQDS
+
+config SYS_BOARD
+ default "ls1043aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1043aqds"
+
+endif
--- /dev/null
+LS1043AQDS BOARD
+M: Mingkai Hu <Mingkai.Hu@freescale.com>
+S: Maintained
+F: board/freescale/ls1043aqds/
+F: include/configs/ls1043aqds.h
+F: configs/ls1043aqds_defconfig
+F: configs/ls1043aqds_nor_ddr3_defconfig
+F: configs/ls1043aqds_nand_defconfig
+F: configs/ls1043aqds_sdcard_ifc_defconfig
--- /dev/null
+#
+# Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ddr.o
+obj-y += eth.o
+obj-y += ls1043aqds.o
--- /dev/null
+Overview
+--------
+The LS1043A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043AQDS provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment.
+
+LS1043A SoC Overview
+--------------------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+ the following functions:
+ - Packet parsing, classification, and distribution (FMan)
+ - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+ - Hardware buffer management for buffer allocation and de-allocation (BMan)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+ - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x QSGMII
+ - Up to 4 x SGMII supporting 1000Mbps
+ - Up to 2 x SGMII supporting 2500Mbps
+ - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+ - Three PCIe 2.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+ - Three high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Serial peripheral interface (SPI) controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+ LS1043AQDS board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - QSGMII
+ - SATA 3.0
+ - XFI
+ - DDR Controller
+ - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
+ -IFC/Local Bus
+ - One in-socket 128 MB NOR flash 16-bit data bus
+ - One 512 MB NAND flash with ECC support
+ - PromJet Port
+ - FPGA connection
+ - USB 3.0
+ - Three high speed USB 3.0 ports
+ - First USB 3.0 port configured as Host with Type-A connector
+ - The other two USB 3.0 ports configured as OTG with micro-AB connector
+ - SDHC port connects directly to an adapter card slot, featuring:
+ - Optional clock feedback paths, and optional high-speed voltage translation assistance
+ - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
+ - eMMC memory devices
+ - DSPI: Onboard support for three SPI flash memory devices
+ - 4 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - Two 4-pin serial ports at up to 115.2 Kbit/s
+ - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address End Address Description Size
+0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
+0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
+0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
+0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
+0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 3) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->cpo_override = pbsp->cpo_override;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for %lu MT/s\n",
+ ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ popts->cswl_override = DDR_CSWL_CS0;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
+ puts("Initializing DDR....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+#endif
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+ fsl_dp_ddr_restore();
+#endif
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo_override;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+#ifdef CONFIG_SYS_FSL_DDR4
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,},
+ {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
+ {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+#else
+#error DDR type not defined
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <fsl_dtsec.h>
+#include <malloc.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "ls1043aqds_qixis.h"
+
+#define EMI_NONE 0xFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT4 5
+#define EMI2 6
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "LS1043AQDS_MDIO_RGMII1",
+ "LS1043AQDS_MDIO_RGMII2",
+ "LS1043AQDS_MDIO_SLOT1",
+ "LS1043AQDS_MDIO_SLOT2",
+ "LS1043AQDS_MDIO_SLOT3",
+ "LS1043AQDS_MDIO_SLOT4",
+ "NULL",
+};
+
+/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {1, 2, 3, 4};
+
+static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name;
+
+ if (muxval > EMI2)
+ return NULL;
+
+ name = ls1043aqds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct ls1043aqds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void ls1043aqds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct ls1043aqds_mdio *priv = bus->priv;
+
+ ls1043aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls1043aqds_mdio *priv = bus->priv;
+
+ ls1043aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad,
+ regnum, value);
+}
+
+static int ls1043aqds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls1043aqds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct ls1043aqds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate ls1043aqds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate ls1043aqds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls1043aqds_mdio_read;
+ bus->write = ls1043aqds_mdio_write;
+ bus->reset = ls1043aqds_mdio_reset;
+ sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ struct fixed_link f_link;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ if (port == FM1_DTSEC9) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s1_p1");
+ } else if (port == FM1_DTSEC2) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s2_p1");
+ } else if (port == FM1_DTSEC5) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s3_p1");
+ } else if (port == FM1_DTSEC6) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s4_p1");
+ }
+ } else if (fm_info_get_enet_if(port) ==
+ PHY_INTERFACE_MODE_SGMII_2500) {
+ /* 2.5G SGMII interface */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 1000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for 2.5G SGMII */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "sgmii-2500");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+ switch (mdio_mux[port]) {
+ case EMI1_SLOT1:
+ switch (port) {
+ case FM1_DTSEC1:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p1");
+ break;
+ case FM1_DTSEC2:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p2");
+ break;
+ case FM1_DTSEC5:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p3");
+ break;
+ case FM1_DTSEC6:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p4");
+ break;
+ default:
+ break;
+ }
+ break;
+ case EMI1_SLOT2:
+ switch (port) {
+ case FM1_DTSEC1:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p1");
+ break;
+ case FM1_DTSEC2:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p2");
+ break;
+ case FM1_DTSEC5:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p3");
+ break;
+ case FM1_DTSEC6:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p4");
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ fdt_delprop(fdt, offset, "phy-connection-type");
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "qsgmii");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
+ port == FM1_10GEC1) {
+ /* XFI interface */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ break;
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi1_slot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x2555:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ break;
+ case 0x4555:
+ case 0x4558:
+ /* QSGMII on lane A, MAC 1/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC1,
+ QSGMII_CARD_PORT1_PHY_ADDR_S1);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ QSGMII_CARD_PORT2_PHY_ADDR_S1);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ QSGMII_CARD_PORT3_PHY_ADDR_S1);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ QSGMII_CARD_PORT4_PHY_ADDR_S1);
+ break;
+ case 0x1355:
+ /* SGMII on lane B, MAC 2*/
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x2355:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ /* SGMII on lane B, MAC 2*/
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x3335:
+ /* SGMII on lane C, MAC 5 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ case 0x3355:
+ case 0x3358:
+ /* SGMII on lane B, MAC 2 */
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ case 0x3555:
+ case 0x3558:
+ /* SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x1455:
+ /* QSGMII on lane B, MAC 1/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC1,
+ QSGMII_CARD_PORT1_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ QSGMII_CARD_PORT2_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ QSGMII_CARD_PORT3_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ QSGMII_CARD_PORT4_PHY_ADDR_S2);
+ break;
+ case 0x2455:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ /* QSGMII on lane B, MAC 1/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC1,
+ QSGMII_CARD_PORT1_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ QSGMII_CARD_PORT2_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ QSGMII_CARD_PORT3_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ QSGMII_CARD_PORT4_PHY_ADDR_S2);
+ break;
+ case 0x2255:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ /* 2.5G SGMII on lane B, MAC 2 */
+ fm_info_set_phy_address(FM1_DTSEC2, 2);
+ break;
+ case 0x3333:
+ /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC9,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ default:
+ printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_2500_FM1_DTSEC1 + idx);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_A);
+ }
+
+ if (lane < 0)
+ break;
+
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII1;
+ else if (i == FM1_DTSEC4)
+ mdio_mux[i] = EMI1_RGMII2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <spl.h>
+
+#include "../common/qixis.h"
+#include "ls1043aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ MUX_TYPE_GPIO,
+};
+
+/* LS1043AQDS serdes mux */
+#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
+#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
+#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
+#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
+#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
+#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
+#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
+#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
+
+int checkboard(void)
+{
+ char buf[64];
+#ifndef CONFIG_SD_BOOT
+ u8 sw;
+#endif
+
+ puts("Board: LS1043AQDS, boot from ");
+
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#else
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0x15)
+ printf("IFCCard\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ printf("FPGA: v%d (%s), build %d\n",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+
+ return 0;
+}
+
+bool if_board_diff_clk(void)
+{
+ u8 diff_conf = QIXIS_READ(brdcfg[11]);
+
+ return diff_conf & 0x40;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0f) {
+ case QIXIS_SYSCLK_64:
+ return 64000000;
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ if (if_board_diff_clk())
+ return get_board_sys_clk();
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+
+ return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * When resuming from deep sleep, the I2C channel may not be
+ * in the default channel. So, switch to the default channel
+ * before accessing DDR SPD.
+ */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+void board_retimer_init(void)
+{
+ u8 reg;
+
+ /* Retimer is connected to I2C1_CH7_CH5 */
+ reg = I2C_MUX_CH7;
+ i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
+ reg = I2C_MUX_CH5;
+ i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
+
+ /* Access to Control/Shared register */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Read device revision and ID */
+ i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
+ debug("Retimer version id = 0x%x\n", reg);
+
+ /* Enable Broadcast. All writes target all channel register sets */
+ reg = 0x0c;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Reset Channel Registers */
+ i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+ reg |= 0x4;
+ i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+
+ /* Enable override divider select and Enable Override Output Mux */
+ i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
+ reg |= 0x24;
+ i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
+
+ /* Select VCO Divider to full rate (000) */
+ i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
+ reg &= 0x8f;
+ i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
+
+ /* Selects active PFD MUX Input as Re-timed Data (001) */
+ i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
+ reg &= 0x3f;
+ reg |= 0x20;
+ i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
+ reg = 0xb2;
+ i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
+ reg = 0xcd;
+ i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+#endif
+
+int config_board_mux(int ctrl_type)
+{
+ u8 reg14;
+
+ reg14 = QIXIS_READ(brdcfg[14]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_GPIO:
+ reg14 = (reg14 & (~0x30)) | 0x20;
+ break;
+ default:
+ puts("Unsupported mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[14], reg14);
+
+ return 0;
+}
+
+int config_serdes_mux(void)
+{
+ return 0;
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ if (hwconfig("gpio"))
+ config_board_mux(MUX_TYPE_GPIO);
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+ CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to enable barrier
+ * transaction */
+ out_le32(&cci->ctrl_ord,
+ CCI400_CTRLORD_EN_BARRIER);
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ board_retimer_init();
+
+#ifdef CONFIG_SYS_FSL_SERDES
+ config_serdes_mux();
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+ return 0;
+}
+#endif
+
+u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
--- /dev/null
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xe0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+#define QIXIS_SYSCLK_64 0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100 0x0
+#define QIXIS_SDCLK1_125 0x1
+#define QIXIS_SDCLK1_165 0x2
+#define QIXIS_SDCLK1_100_SP 0x3
+
+#endif
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable IFC; disable QSPI
+0810000f 0c000000 00000000 00000000
+14550002 80004012 60040000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
int board_early_init_f(void)
{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 usb_pwrfault;
+
fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ out_be32(&scfg->rcwpmuxcr0, 0x3333);
+ out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+ usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED <<
+ SCFG_USBPWRFAULT_USB1_SHIFT);
+ out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
return 0;
}
-if TARGET_LS2085A_EMU
+if TARGET_LS2080A_EMU
config SYS_BOARD
- default "ls2085a"
+ default "ls2080a"
config SYS_VENDOR
default "freescale"
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085a_emu"
+ default "ls2080a_emu"
endif
-if TARGET_LS2085A_SIMU
+if TARGET_LS2080A_SIMU
config SYS_BOARD
- default "ls2085a"
+ default "ls2080a"
config SYS_VENDOR
default "freescale"
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085a_simu"
+ default "ls2080a_simu"
endif
--- /dev/null
+LS2080A BOARD
+M: York Sun <yorksun@freescale.com>
+S: Maintained
+F: board/freescale/ls2080a/
+F: include/configs/ls2080a_emu.h
+F: configs/ls2080a_emu_defconfig
+F: include/configs/ls2080a_simu.h
+F: configs/ls2080a_simu_defconfig
+F: configs/ls2085a_emu_defconfig
+F: configs/ls2085a_simu_defconfig
--- /dev/null
+#
+# Copyright 2014-15 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2080a.o
+obj-y += ddr.o
-Freescale ls2085a_emu
+Freescale ls2080a_emu
This is a emulator target with limited peripherals.
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
popts->burst_length = DDR_BL8;
popts->bstopre = 0; /* enable auto precharge */
}
+#endif
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
+#endif
}
int dram_init(void)
-if TARGET_LS2085ARDB
+if TARGET_LS2080AQDS
config SYS_BOARD
- default "ls2085ardb"
+ default "ls2080aqds"
config SYS_VENDOR
default "freescale"
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085ardb"
+ default "ls2080aqds"
endif
--- /dev/null
+LS2080A BOARD
+M: Prabhakar Kushwaha <prabhakar@freescale.com>
+S: Maintained
+F: board/freescale/ls2080aqds/
+F: board/freescale/ls2080a/ls2080aqds.c
+F: include/configs/ls2080aqds.h
+F: configs/ls2080aqds_defconfig
+F: configs/ls2080aqds_nand_defconfig
+F: configs/ls2085aqds_defconfig
+F: configs/ls2085aqds_nand_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ls2085aqds.o
+obj-y += ls2080aqds.o
obj-y += ddr.o
obj-y += eth.o
Overview
--------
-The LS2085A Development System (QDS) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
-Layerscape Architecture processor. The LS2085AQDS provides validation and
-SW development platform for the Freescale LS2085A processor series, with
+The LS2080A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+Layerscape Architecture processor. The LS2080AQDS provides validation and
+SW development platform for the Freescale LS2080A processor series, with
a complete debugging environment.
-LS2085A SoC Overview
+LS2080A SoC Overview
------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
- LS2085AQDS board Overview
+ LS2080AQDS board Overview
-----------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
-Mapping DPMACx to PHY during QSGMII
+Mapping DPMACx to PHY during SGMII
DPMAC1 -> PHY1-P0
DPMAC2 -> PHY2-P0
DPMAC3 -> PHY3-P0
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
int slot;
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
pdimm[slot].dq_mapping[16] = 0;
pdimm[slot].dq_mapping[17] = 0;
}
+#endif
/* To work at higher than 1333MT/s */
popts->half_strength_driver_enable = 0;
/*
#include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"
#ifdef CONFIG_FSL_MC_ENET
- /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D, E, F, G, H
* Bank 2 -> Lanes A,B, C, D, E, F, G, H
*/
- /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
+ /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
* means that the mapping must be determined dynamically, or that the lane
* maps to something other than a board slot.
*/
#define SFP_TX 0
static const char * const mdio_names[] = {
- "LS2085A_QDS_MDIO0",
- "LS2085A_QDS_MDIO1",
- "LS2085A_QDS_MDIO2",
- "LS2085A_QDS_MDIO3",
- "LS2085A_QDS_MDIO4",
- "LS2085A_QDS_MDIO5",
+ "LS2080A_QDS_MDIO0",
+ "LS2080A_QDS_MDIO1",
+ "LS2080A_QDS_MDIO2",
+ "LS2080A_QDS_MDIO3",
+ "LS2080A_QDS_MDIO4",
+ "LS2080A_QDS_MDIO5",
DEFAULT_WRIOP_MDIO2_NAME,
};
-struct ls2085a_qds_mdio {
+struct ls2080a_qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
int i, j, ret;
int dpmac_id = 0, dpmac, mii_bus = 0;
unsigned short value;
- char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"};
+ char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- const char *dev = "LS2085A_QDS_MDIO0";
+ const char *dev = "LS2080A_QDS_MDIO0";
int ret = 0;
unsigned short value;
return;
}
-static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
+static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
- const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
+ const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return bus;
}
-static void ls2085a_qds_enable_SFP_TX(u8 muxval)
+static void ls2080a_qds_enable_SFP_TX(u8 muxval)
{
u8 brdcfg9;
QIXIS_WRITE(brdcfg[9], brdcfg9);
}
-static void ls2085a_qds_mux_mdio(u8 muxval)
+static void ls2080a_qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
}
}
-static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
+static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
int devad, int regnum)
{
- struct ls2085a_qds_mdio *priv = bus->priv;
+ struct ls2080a_qds_mdio *priv = bus->priv;
- ls2085a_qds_mux_mdio(priv->muxval);
+ ls2080a_qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
-static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
- struct ls2085a_qds_mdio *priv = bus->priv;
+ struct ls2080a_qds_mdio *priv = bus->priv;
- ls2085a_qds_mux_mdio(priv->muxval);
+ ls2080a_qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
-static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
+static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
{
- struct ls2085a_qds_mdio *priv = bus->priv;
+ struct ls2080a_qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
-static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
+static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
{
- struct ls2085a_qds_mdio *pmdio;
+ struct ls2080a_qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
- printf("Failed to allocate ls2085a_qds MDIO bus\n");
+ printf("Failed to allocate ls2080a_qds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
- printf("Failed to allocate ls2085a_qds private data\n");
+ printf("Failed to allocate ls2080a_qds private data\n");
free(bus);
return -1;
}
- bus->read = ls2085a_qds_mdio_read;
- bus->write = ls2085a_qds_mdio_write;
- bus->reset = ls2085a_qds_mdio_reset;
- sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
+ bus->read = ls2080a_qds_mdio_read;
+ bus->write = ls2080a_qds_mdio_write;
+ bus->reset = ls2080a_qds_mdio_reset;
+ sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
serdes1_prtcl);
break;
default:
- printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
+ printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+ __func__, serdes1_prtcl);
break;
}
}
break;
default:
- printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
+ printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+ __func__ , serdes2_prtcl);
break;
}
}
-void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
{
int lane, slot;
struct mii_dev *bus;
}
break;
default:
- printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
+ printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+ __func__ , serdes1_prtcl);
break;
}
}
break;
default:
- printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
+ printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+ __func__, serdes2_prtcl);
break;
}
}
-void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
{
int lane = 0, slot;
struct mii_dev *bus;
qsgmii_configure_repeater(dpmac_id);
}
-void ls2085a_handle_phy_interface_xsgmii(int i)
+void ls2080a_handle_phy_interface_xsgmii(int i)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
* error.
*/
wriop_set_phy_address(i, i + 4);
- ls2085a_qds_enable_SFP_TX(SFP_TX);
+ ls2080a_qds_enable_SFP_TX(SFP_TX);
break;
default:
fm_memac_mdio_init(bis, memac_mdio1_info);
/* Register the muxing front-ends to the MDIO buses */
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
- ls2085a_handle_phy_interface_qsgmii(i);
+ ls2080a_handle_phy_interface_qsgmii(i);
break;
case PHY_INTERFACE_MODE_SGMII:
- ls2085a_handle_phy_interface_sgmii(i);
+ ls2080a_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_XGMII:
- ls2085a_handle_phy_interface_xsgmii(i);
+ ls2080a_handle_phy_interface_xsgmii(i);
break;
default:
break;
#include <hwconfig.h>
#include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
+#endif
}
int dram_init(void)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+ int err;
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
- fsl_mc_ldpaa_exit(bd);
+ err = fsl_mc_ldpaa_exit(bd);
+ if (err)
+ return err;
#endif
return 0;
-if TARGET_LS2085AQDS
+if TARGET_LS2080ARDB
config SYS_BOARD
- default "ls2085aqds"
+ default "ls2080ardb"
config SYS_VENDOR
default "freescale"
default "fsl-layerscape"
config SYS_CONFIG_NAME
- default "ls2085aqds"
+ default "ls2080ardb"
endif
--- /dev/null
+LS2080A BOARD
+M: Prabhakar Kushwaha <prabhakar@freescale.com>
+S: Maintained
+F: board/freescale/ls2080ardb/
+F: board/freescale/ls2080a/ls2080ardb.c
+F: include/configs/ls2080ardb.h
+F: configs/ls2080ardb_defconfig
+F: configs/ls2080ardb_nand_defconfig
+F: configs/ls2085ardb_defconfig
+F: configs/ls2085ardb_nand_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ls2085ardb.o eth_ls2085rdb.o
+obj-y += ls2080ardb.o eth_ls2080rdb.o
obj-y += ddr.o
Overview
--------
-The LS2085A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
-LS2085A SoC Overview
+LS2080A SoC Overview
------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
- LS2085ARDB board Overview
+ LS2080ARDB board Overview
-----------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
int slot;
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
pdimm[slot].dq_mapping[16] = 0;
pdimm[slot].dq_mapping[17] = 0;
}
+#endif
/* To work at higher than 1333MT/s */
popts->half_strength_driver_enable = 0;
/*
break;
default:
- printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+ printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
srds_s1);
break;
}
#include <asm/arch/soc.h>
#include "../common/qixis.h"
-#include "ls2085ardb_qixis.h"
+#include "ls2080ardb_qixis.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
+#endif
}
int dram_init(void)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+ int err;
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
- fsl_mc_ldpaa_exit(bd);
+ err = fsl_mc_ldpaa_exit(bd);
+ if (err)
+ return err;
#endif
return 0;
+++ /dev/null
-LS2085A BOARD
-M: York Sun <yorksun@freescale.com>
-S: Maintained
-F: board/freescale/ls2085a/
-F: include/configs/ls2085a_emu.h
-F: configs/ls2085a_emu_defconfig
-F: include/configs/ls2085a_simu.h
-F: configs/ls2085a_simu_defconfig
+++ /dev/null
-#
-# Copyright 2014 Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ls2085a.o
-obj-y += ddr.o
+++ /dev/null
-LS2085A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
-S: Maintained
-F: board/freescale/ls2085aqds/
-F: board/freescale/ls2085a/ls2085aqds.c
-F: include/configs/ls2085aqds.h
-F: configs/ls2085aqds_defconfig
-F: configs/ls2085aqds_nand_defconfig
+++ /dev/null
-LS2085A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
-S: Maintained
-F: board/freescale/ls2085ardb/
-F: board/freescale/ls2085a/ls2085ardb.c
-F: include/configs/ls2085ardb.h
-F: configs/ls2085ardb_defconfig
-F: configs/ls2085ardb_nand_defconfig
config SYS_BOARD
default "lwmon5"
+config SYS_VENDOR
+ default "liebherr"
+
config SYS_CONFIG_NAME
default "lwmon5"
LWMON5 BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
-F: board/lwmon5/
+F: board/liebherr/lwmon5/
F: include/configs/lwmon5.h
F: configs/lwmon5_defconfig
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if TARGET_NSA310S
+
+config SYS_BOARD
+ default "nsa310s"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa310s"
+
+endif
--- /dev/null
+NSA310S BOARD
+M: Gerald Kerma <dreagle@doukki.net>
+M: Tony Dinh <mibodhi@gmail.com>
+M: Luka Perkov <luka.perkov@sartura.hr>
+S: Maintained
+F: board/zyxel/nsa310s/
+F: include/configs/nsa310s.h
+F: configs/nsa310s_defconfig
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa310s.o
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD01400 0x43010c30
+DATA 0xFFD01404 0x39543000
+DATA 0xFFD01408 0x22125451
+DATA 0xFFD0140C 0x00000833
+DATA 0xFFD01410 0x0000000C
+DATA 0xFFD01414 0x00000000
+DATA 0xFFD01418 0x00000000
+DATA 0xFFD0141C 0x00000652
+DATA 0xFFD01420 0x00000004
+DATA 0xFFD01424 0x0000F17F
+DATA 0xFFD01428 0x00085520
+DATA 0xFFD0147c 0x00008552
+DATA 0xFFD01504 0x0FFFFFF1
+DATA 0xFFD01508 0x10000000
+DATA 0xFFD0150C 0x00000000
+DATA 0xFFD01514 0x00000000
+DATA 0xFFD0151C 0x00000000
+DATA 0xFFD01494 0x00010000
+DATA 0xFFD01498 0x00000000
+DATA 0xFFD0149C 0x0000E403
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0x0 0x0
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+#include "nsa310s.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
+ NSA310S_OE_LOW, NSA310S_OE_HIGH);
+
+ /* (all LEDs & power off active high) */
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ u16 reg;
+ u16 phyaddr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* read PHY dev address */
+ if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
+ printf("could not read PHY dev address\n");
+ return;
+ }
+
+ /* set RGMII delay */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+ miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
+ reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
+ miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* reset PHY */
+ if (miiphy_reset(name, phyaddr))
+ return;
+
+ /*
+ * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
+ * and has an MCU attached to the LED[2] via tristate interrupt
+ */
+
+ /* switch to LED register page */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
+ /* read out LED polarity register */
+ miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
+ /* clear 4, set 5 - LED2 low, tri-state */
+ reg &= ~(MV88E1318_LED2_4);
+ reg |= (MV88E1318_LED2_5);
+ /* write back LED polarity register */
+ miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
+ /* jump back to page 0, per the PHY chip documenation. */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* set PHY back to auto-negotiation mode */
+ miiphy_write(name, phyaddr, 0x4, 0x1e1);
+ miiphy_write(name, phyaddr, 0x9, 0x300);
+ /* downshift */
+ miiphy_write(name, phyaddr, 0x10, 0x3860);
+ miiphy_write(name, phyaddr, 0x0, 0x9140);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __NSA310S_H
+#define __NSA310S_H
+
+/* low GPIO's */
+#define HDD1_GREEN_LED (1 << 16)
+#define HDD1_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_POWER (1 << 21)
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_ORANGE_LED (1 << 29)
+
+#define COPY_GREEN_LED (1 << 22)
+#define COPY_RED_LED (1 << 23)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA310S_OE_LOW (~(0))
+#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define HDD2_GREEN_LED (1 << 2)
+#define HDD2_POWER (1 << 1)
+
+#define NSA310S_OE_HIGH (~(0))
+#define NSA310S_VAL_HIGH (HDD2_POWER)
+
+/* PHY related */
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_MAC_CTRL_PG 2
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_RGMII_TX_CTRL (1 << 4)
+#define MV88E1318_RGMII_RX_CTRL (1 << 5)
+#define MV88E1318_LED_PG 3
+#define MV88E1318_LED_POL_REG 17
+#define MV88E1318_LED2_4 (1 << 4)
+#define MV88E1318_LED2_5 (1 << 5)
+
+#endif /* __NSA310S_H */
return *line_length * panel_info.vl_row;
}
+/*
+ * Implement a weak default function for boards that optionally
+ * need to skip the lcd console initialization.
+ */
+__weak int board_lcd_console_skip(void)
+{
+ /* As default, don't skip cfb init */
+ return 0;
+}
+
int drv_lcd_init(void)
{
struct stdio_dev lcddev;
lcd_init(lcd_base);
+ if (board_lcd_console_skip())
+ return 0;
+
/* Device initialization */
memset(&lcddev, 0, sizeof(lcddev));
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_OF_CONTROL=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080A_EMU=y
+CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080A_SIMU=y
+CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_EMU=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
+CONFIG_TARGET_LS2080A_EMU=y
+CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_SIMU=y
-CONFIG_SYS_EXTRA_OPTIONS="SIMU"
+CONFIG_TARGET_LS2080A_SIMU=y
+CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080AQDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080AQDS=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080ARDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080ARDB=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_TARGET_NSA310S=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_PROMPT="nsa310s => "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_USB=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
+CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
-Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like
+Freescale ARM64 SoCs like LS2080A have ARM TrustZone components like
TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
Address Space Controller).
privilege mode), but still some configurations of these peripherals
might be required while the bootloader is executing in EL3 privilege
mode. The following sections define how to turn on these features for
-LS2085A like SoCs.
+LS2080A like SoCs.
TZPC-BP147 (TrustZone Protection Controller)
============================================
goto step2;
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
/* A008336 only applies to general DDR controllers */
if ((ctrl_num == 0) || (ctrl_num == 1))
#endif
ddr_out32(eddrtqcr1, 0x63b30002);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
/* A008514 only applies to DP-DDR controler */
if (ctrl_num == 2)
#endif
if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
puts("Running BIST test. This will take a while...");
cs0_config = ddr_in32(&ddr->cs0_config);
+ cs0_bnds = ddr_in32(&ddr->cs0_bnds);
+ cs1_bnds = ddr_in32(&ddr->cs1_bnds);
+ cs2_bnds = ddr_in32(&ddr->cs2_bnds);
+ cs3_bnds = ddr_in32(&ddr->cs3_bnds);
if (cs0_config & CTLR_INTLV_MASK) {
- cs0_bnds = ddr_in32(&cs0_bnds);
- cs1_bnds = ddr_in32(&cs1_bnds);
- cs2_bnds = ddr_in32(&cs2_bnds);
- cs3_bnds = ddr_in32(&cs3_bnds);
/* set bnds to non-interleaving */
- ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
- ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
- ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
- ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
}
ddr_out32(&ddr->mtp1, BIST_PATTERN1);
ddr_out32(&ddr->mtp2, BIST_PATTERN1);
if (cs0_config & CTLR_INTLV_MASK) {
/* restore bnds registers */
- ddr_out32(&cs0_bnds, cs0_bnds);
- ddr_out32(&cs1_bnds, cs1_bnds);
- ddr_out32(&cs2_bnds, cs2_bnds);
- ddr_out32(&cs3_bnds, cs3_bnds);
+ ddr_out32(&ddr->cs0_bnds, cs0_bnds);
+ ddr_out32(&ddr->cs1_bnds, cs1_bnds);
+ ddr_out32(&ddr->cs2_bnds, cs2_bnds);
+ ddr_out32(&ddr->cs3_bnds, cs3_bnds);
}
}
#endif
info.board_need_mem_reset = board_need_mem_reset;
info.board_mem_reset = board_assert_mem_reset;
info.board_mem_de_reset = board_deassert_mem_reset;
+ remove_unused_controllers(&info);
return __fsl_ddr_sdram(&info);
}
ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
}
#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
+
+void remove_unused_controllers(fsl_ddr_info_t *info)
+{
+#ifdef CONFIG_FSL_LSCH3
+ int i;
+ u64 nodeid;
+ void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
+ bool ddr0_used = false;
+ bool ddr1_used = false;
+
+ for (i = 0; i < 8; i++) {
+ nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
+ if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
+ ddr0_used = true;
+ } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
+ ddr1_used = true;
+ } else {
+ printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
+ nodeid);
+ }
+ hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
+ }
+ if (!ddr0_used && !ddr1_used) {
+ printf("Invalid configuration in HN-F SAM control\n");
+ return;
+ }
+
+ if (!ddr0_used && info->first_ctrl == 0) {
+ info->first_ctrl = 1;
+ info->num_ctrls = 1;
+ debug("First DDR controller disabled\n");
+ return;
+ }
+
+ if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
+ info->num_ctrls = 1;
+ debug("Second DDR controller disabled\n");
+ }
+#endif
+}
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
-{
+/* socfpga implmentation specific drver private data */
+struct dwmci_socfpga_priv_data {
unsigned int drvsel;
unsigned int smplsel;
+};
+
+static void socfpga_dwmci_clksel(struct dwmci_host *host)
+{
+ struct dwmci_socfpga_priv_data *priv = host->priv;
/* Disable SDMMC clock. */
clrbits_le32(&clock_manager_base->per_pll.en,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
- /* Configures drv_sel and smpl_sel */
- drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
- smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
-
- debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
- writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
+ debug("%s: drvsel %d smplsel %d\n", __func__,
+ priv->drvsel, priv->smplsel);
+ writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
&system_manager_base->sdmmcgrp_ctrl);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
const unsigned long clk = cm_get_mmc_controller_clk_hz();
struct dwmci_host *host;
+ struct dwmci_socfpga_priv_data *priv;
fdt_addr_t reg_base;
int bus_width, fifo_depth;
if (!host)
return -ENOMEM;
+ /* Allocate the priv */
+ priv = calloc(1, sizeof(*priv));
+ if (!priv) {
+ free(host);
+ return -ENOMEM;
+ }
+
host->name = "SOCFPGA DWMMC";
host->ioaddr = (void *)reg_base;
host->buswidth = bus_width;
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+ priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
+ priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
+ host->priv = priv;
return add_dwmci(host, host->bus_hz, 400000);
}
dpmng.o \
dprc.o \
dpbp.o \
- dpni.o
+ dpni.o \
+ dpmac.o
obj-y += dpio/
return mc_send_command(mc_io, &cmd);
}
+int dpbp_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpbp_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ (void)(cfg); /* unused */
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
+ cmd_flags,
+ 0);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpbp_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpbp_enable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
return mc_send_command(mc_io, &cmd);
}
+int dpio_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpio_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPIO_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpio_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpio_enable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
--- /dev/null
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpmac.h>
+
+int dpmac_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpmac_id,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
+ cmd_flags,
+ 0);
+ DPMAC_CMD_OPEN(cmd, dpmac_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return err;
+}
+
+int dpmac_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpmac_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPMAC_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpmac_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPMAC_RSP_GET_ATTRIBUTES(cmd, attr);
+
+ return 0;
+}
+
+int dpmac_mdio_read(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ,
+ cmd_flags,
+ token);
+ DPMAC_CMD_MDIO_READ(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPMAC_RSP_MDIO_READ(cmd, cfg->data);
+
+ return 0;
+}
+
+int dpmac_mdio_write(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE,
+ cmd_flags,
+ token);
+ DPMAC_CMD_MDIO_WRITE(cmd, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+ int err = 0;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPMAC_RSP_GET_LINK_CFG(cmd, cfg);
+
+ return 0;
+}
+
+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_state *link_state)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
+ cmd_flags,
+ token);
+ DPMAC_CMD_SET_LINK_STATE(cmd, link_state);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_counter(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpmac_counter type,
+ uint64_t *counter)
+{
+ struct mc_command cmd = { 0 };
+ int err = 0;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
+ cmd_flags,
+ token);
+ DPMAC_CMD_GET_COUNTER(cmd, type);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPMAC_RSP_GET_COUNTER(cmd, *counter);
+
+ return 0;
+}
return mc_send_command(mc_io, &cmd);
}
+int dpni_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpni_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPNI_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpni_set_pools(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
return mc_send_command(mc_io, &cmd);
}
+int dprc_create_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dprc_cfg *cfg,
+ int *child_container_id,
+ uint64_t *child_portal_paddr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ DPRC_CMD_CREATE_CONTAINER(cmd, cfg);
+
+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id,
+ *child_portal_paddr);
+
+ return 0;
+}
+
+int dprc_destroy_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int child_container_id)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
+ cmd_flags,
+ token);
+ DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dprc_reset_container(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
#include <fsl-mc/fsl_dpmng.h>
#include <fsl-mc/fsl_dprc.h>
#include <fsl-mc/fsl_dpio.h>
+#include <fsl-mc/fsl_dpni.h>
#include <fsl-mc/fsl_qbman_portal.h>
+#include <fsl-mc/ldpaa_wriop.h>
#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
DECLARE_GLOBAL_DATA_PTR;
-static int mc_boot_status;
-struct fsl_mc_io *dflt_mc_io = NULL;
+static int mc_boot_status = -1;
+static int mc_dpl_applied = -1;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+static int mc_aiop_applied = -1;
+#endif
+struct fsl_mc_io *root_mc_io = NULL;
+struct fsl_mc_io *dflt_mc_io = NULL; /* child container */
+uint16_t root_dprc_handle = 0;
uint16_t dflt_dprc_handle = 0;
+int child_dprc_id;
struct fsl_dpbp_obj *dflt_dpbp = NULL;
struct fsl_dpio_obj *dflt_dpio = NULL;
-uint16_t dflt_dpio_handle = 0;
+struct fsl_dpni_obj *dflt_dpni = NULL;
#ifdef DEBUG
void dump_ram_words(const char *title, void *addr)
* Returns 0 on success and a negative errno on error.
* task fail.
**/
-int parse_mc_firmware_fit_image(const void **raw_image_addr,
+int parse_mc_firmware_fit_image(u64 mc_fw_addr,
+ const void **raw_image_addr,
size_t *raw_image_size)
{
int format;
size_t size;
const char *uname = "firmware";
- /* Check if the image is in NOR flash */
-#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
- fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
-#endif
+ fit_hdr = (void *)mc_fw_addr;
/* Check if Image is in FIT format */
format = genimg_get_format(fit_hdr);
if (format != IMAGE_FORMAT_FIT) {
- printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
+ printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
return -EINVAL;
}
if (!fit_check_format(fit_hdr)) {
- printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
+ printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
return -EINVAL;
}
node_offset = fit_image_get_node(fit_hdr, uname);
if (node_offset < 0) {
- printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
+ printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
return -ENOENT;
}
/* Verify MC firmware image */
if (!(fit_image_verify(fit_hdr, node_offset))) {
- printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
+ printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
return -EINVAL;
}
return 0;
}
-static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
+static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
{
u64 mc_dpc_offset;
#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
/*
* Get address and size of the DPC blob stored in flash:
*/
-#ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR
- dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined"
-#endif
+ dpc_fdt_hdr = (void *)mc_dpc_addr;
error = fdt_check_header(dpc_fdt_hdr);
if (error != 0) {
return 0;
}
-static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
+static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
{
u64 mc_dpl_offset;
#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
/*
* Get address and size of the DPL blob stored in flash:
*/
-#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
- dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
-#endif
+ dpl_fdt_hdr = (void *)mc_dpl_addr;
error = fdt_check_header(dpl_fdt_hdr);
if (error != 0) {
return timeout_ms;
}
-#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
-static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size)
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+static int load_mc_aiop_img(u64 aiop_fw_addr)
{
+ u64 mc_ram_addr = mc_get_dram_addr();
+#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
void *aiop_img;
+#endif
/*
* Load the MC AIOP image in the MC private DRAM block:
*/
- aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR;
+#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
+ printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
+ CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+#else
+ aiop_img = (void *)aiop_fw_addr;
mc_copy_image("MC AIOP image",
(u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+#endif
+ mc_aiop_applied = 0;
return 0;
}
#endif
+
static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
{
u32 reg_gsr;
return 0;
}
-int mc_init(void)
+int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
{
int error = 0;
int portal_id = 0;
struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
- u64 mc_ram_addr;
+ u64 mc_ram_addr = mc_get_dram_addr();
u32 reg_gsr;
u32 reg_mcfbalr;
#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
u8 mc_ram_num_256mb_blocks;
size_t mc_ram_size = mc_get_dram_block_size();
- /*
- * The MC private DRAM block was already carved at the end of DRAM
- * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
- */
- if (gd->bd->bi_dram[1].start) {
- mc_ram_addr =
- gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
- } else {
- mc_ram_addr =
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
- }
error = calculate_mc_private_ram_params(mc_ram_addr,
mc_ram_size,
#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
#else
- error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
+ error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
+ &raw_image_size);
if (error != 0)
goto out;
/*
#endif
dump_ram_words("firmware", (void *)mc_ram_addr);
- error = load_mc_dpc(mc_ram_addr, mc_ram_size);
+ error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
if (error != 0)
goto out;
- error = load_mc_dpl(mc_ram_addr, mc_ram_size);
- if (error != 0)
- goto out;
-
-#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
- error = load_mc_aiop_img(mc_ram_addr, mc_ram_size);
- if (error != 0)
- goto out;
-#endif
-
debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
dump_mc_ccsr_regs(mc_ccsr_regs);
* Initialize the global default MC portal
* And check that the MC firmware is responding portal commands:
*/
- dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
- if (!dflt_mc_io) {
+ root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ if (!root_mc_io) {
printf(" No memory: malloc() failed\n");
return -ENOMEM;
}
- dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
+ root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
- portal_id, dflt_mc_io->mmio_regs);
+ portal_id, root_mc_io->mmio_regs);
- error = mc_get_version(dflt_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
+ error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
if (error != 0) {
printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
error);
mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
reg_gsr & GSR_FS_MASK);
+out:
+ if (error != 0)
+ mc_boot_status = error;
+ else
+ mc_boot_status = 0;
+
+ return error;
+}
+
+int mc_apply_dpl(u64 mc_dpl_addr)
+{
+ struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+ int error = 0;
+ u32 reg_gsr;
+ u64 mc_ram_addr = mc_get_dram_addr();
+ size_t mc_ram_size = mc_get_dram_block_size();
+
+ error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
+ if (error != 0)
+ return error;
+
/*
* Tell the MC to deploy the DPL:
*/
out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
printf("fsl-mc: Deploying data path layout ... ");
error = wait_for_mc(false, ®_gsr);
- if (error != 0)
- goto out;
-out:
- if (error != 0)
- mc_boot_status = error;
- else
- mc_boot_status = 0;
+ if (!error)
+ mc_dpl_applied = 0;
return error;
}
return mc_boot_status;
}
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+int get_aiop_apply_status(void)
+{
+ return mc_aiop_applied;
+}
+#endif
+
+int get_dpl_apply_status(void)
+{
+ return mc_dpl_applied;
+}
+
+/**
+ * Return the MC address of private DRAM block.
+ */
+u64 mc_get_dram_addr(void)
+{
+ u64 mc_ram_addr;
+
+ /*
+ * The MC private DRAM block was already carved at the end of DRAM
+ * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
+ */
+ if (gd->bd->bi_dram[1].start) {
+ mc_ram_addr =
+ gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
+ } else {
+ mc_ram_addr =
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+ }
+
+ return mc_ram_addr;
+}
+
/**
* Return the actual size of the MC private DRAM block.
*/
return dram_block_size;
}
-int dpio_init(struct dprc_obj_desc obj_desc)
+int fsl_mc_ldpaa_init(bd_t *bis)
+{
+ int i;
+
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++)
+ if ((wriop_is_enabled_dpmac(i) == 1) &&
+ (wriop_get_phy_address(i) != -1))
+ ldpaa_eth_init(i, wriop_get_enet_if(i));
+ return 0;
+}
+
+static int dpio_init(void)
{
struct qbman_swp_desc p_des;
struct dpio_attr attr;
+ struct dpio_cfg dpio_cfg;
int err = 0;
dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
if (!dflt_dpio) {
- printf(" No memory: malloc() failed\n");
- return -ENOMEM;
+ printf("No memory: malloc() failed\n");
+ err = -ENOMEM;
+ goto err_malloc;
}
- dflt_dpio->dpio_id = obj_desc.id;
+ dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
+ dpio_cfg.num_priorities = 8;
- err = dpio_open(dflt_mc_io, MC_CMD_NO_FLAGS, obj_desc.id,
- &dflt_dpio_handle);
- if (err) {
- printf("dpio_open() failed\n");
- goto err_open;
+ err = dpio_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpio_cfg,
+ &dflt_dpio->dpio_handle);
+ if (err < 0) {
+ printf("dpio_create() failed: %d\n", err);
+ err = -ENODEV;
+ goto err_create;
}
+ memset(&attr, 0, sizeof(struct dpio_attr));
err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle, &attr);
- if (err) {
- printf("dpio_get_attributes() failed %d\n", err);
+ dflt_dpio->dpio_handle, &attr);
+ if (err < 0) {
+ printf("dpio_get_attributes() failed: %d\n", err);
goto err_get_attr;
}
- err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
- if (err) {
+ dflt_dpio->dpio_id = attr.id;
+#ifdef DEBUG
+ printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+#endif
+
+ err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ if (err < 0) {
printf("dpio_enable() failed %d\n", err);
goto err_get_enable;
}
return 0;
err_get_swp_init:
+ dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_get_enable:
- dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
-err_get_attr:
- dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
-err_open:
free(dflt_dpio);
+err_get_attr:
+ dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+err_create:
+err_malloc:
return err;
}
-int dpbp_init(struct dprc_obj_desc obj_desc)
+static int dpio_exit(void)
{
- dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
- if (!dflt_dpbp) {
+ int err;
+
+ err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ if (err < 0) {
+ printf("dpio_disable() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ if (err < 0) {
+ printf("dpio_destroy() failed: %d\n", err);
+ goto err;
+ }
+
+#ifdef DEBUG
+ printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+#endif
+
+ if (dflt_dpio)
+ free(dflt_dpio);
+
+ return 0;
+err:
+ return err;
+}
+
+static int dprc_init(void)
+{
+ int err, child_portal_id, container_id;
+ struct dprc_cfg cfg;
+ uint64_t mc_portal_offset;
+
+ /* Open root container */
+ err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id);
+ if (err < 0) {
+ printf("dprc_get_container_id(): Root failed: %d\n", err);
+ goto err_root_container_id;
+ }
+
+#ifdef DEBUG
+ printf("Root container id = %d\n", container_id);
+#endif
+ err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id,
+ &root_dprc_handle);
+ if (err < 0) {
+ printf("dprc_open(): Root Container failed: %d\n", err);
+ goto err_root_open;
+ }
+
+ if (!root_dprc_handle) {
+ printf("dprc_open(): Root Container Handle is not valid\n");
+ goto err_root_open;
+ }
+
+ cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
+ DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
+ DPRC_CFG_OPT_ALLOC_ALLOWED;
+ cfg.icid = DPRC_GET_ICID_FROM_POOL;
+ cfg.portal_id = 250;
+ err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
+ root_dprc_handle,
+ &cfg,
+ &child_dprc_id,
+ &mc_portal_offset);
+ if (err < 0) {
+ printf("dprc_create_container() failed: %d\n", err);
+ goto err_create;
+ }
+
+ dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ if (!dflt_mc_io) {
+ err = -ENOMEM;
printf(" No memory: malloc() failed\n");
- return -ENOMEM;
+ goto err_malloc;
+ }
+
+ child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
+ dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id);
+#ifdef DEBUG
+ printf("MC portal of child DPRC container: %d, physical addr %p)\n",
+ child_dprc_id, dflt_mc_io->mmio_regs);
+#endif
+
+ err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id,
+ &dflt_dprc_handle);
+ if (err < 0) {
+ printf("dprc_open(): Child container failed: %d\n", err);
+ goto err_child_open;
+ }
+
+ if (!dflt_dprc_handle) {
+ printf("dprc_open(): Child container Handle is not valid\n");
+ goto err_child_open;
}
- dflt_dpbp->dpbp_attr.id = obj_desc.id;
return 0;
+err_child_open:
+ free(dflt_mc_io);
+err_malloc:
+ dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
+ root_dprc_handle, child_dprc_id);
+err_create:
+ dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
+err_root_open:
+err_root_container_id:
+ return err;
}
-int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle)
+static int dprc_exit(void)
{
- int error = 0, state = 0;
- struct dprc_endpoint dpni_endpoint, dpmac_endpoint;
- if (!strcmp(obj_desc.type, "dpbp")) {
- if (!dflt_dpbp) {
- error = dpbp_init(obj_desc);
- if (error < 0)
- printf("dpbp_init failed\n");
- }
- } else if (!strcmp(obj_desc.type, "dpio")) {
- if (!dflt_dpio) {
- error = dpio_init(obj_desc);
- if (error < 0)
- printf("dpio_init failed\n");
- }
- } else if (!strcmp(obj_desc.type, "dpni")) {
- strcpy(dpni_endpoint.type, obj_desc.type);
- dpni_endpoint.id = obj_desc.id;
- error = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS,
- dprc_handle, &dpni_endpoint,
- &dpmac_endpoint, &state);
- if (!strcmp(dpmac_endpoint.type, "dpmac"))
- error = ldpaa_eth_init(obj_desc);
- if (error < 0)
- printf("ldpaa_eth_init failed\n");
+ int err;
+
+ err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
+ if (err < 0) {
+ printf("dprc_close(): Child failed: %d\n", err);
+ goto err;
}
- return error;
+ err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
+ root_dprc_handle, child_dprc_id);
+ if (err < 0) {
+ printf("dprc_destroy_container() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
+ if (err < 0) {
+ printf("dprc_close(): Root failed: %d\n", err);
+ goto err;
+ }
+
+ if (dflt_mc_io)
+ free(dflt_mc_io);
+
+ if (root_mc_io)
+ free(root_mc_io);
+
+ return 0;
+
+err:
+ return err;
}
-int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i)
+static int dpbp_init(void)
{
- int error = 0;
- struct dprc_obj_desc obj_desc;
+ int err;
+ struct dpbp_attr dpbp_attr;
+ struct dpbp_cfg dpbp_cfg;
- memset((void *)&obj_desc, 0x00, sizeof(struct dprc_obj_desc));
+ dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
+ if (!dflt_dpbp) {
+ printf("No memory: malloc() failed\n");
+ err = -ENOMEM;
+ goto err_malloc;
+ }
- error = dprc_get_obj(dflt_mc_io, MC_CMD_NO_FLAGS, dprc_handle,
- i, &obj_desc);
- if (error < 0) {
- printf("dprc_get_obj(i=%d) failed: %d\n",
- i, error);
- return error;
+ dpbp_cfg.options = 512;
+
+ err = dpbp_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpbp_cfg,
+ &dflt_dpbp->dpbp_handle);
+
+ if (err < 0) {
+ err = -ENODEV;
+ printf("dpbp_create() failed: %d\n", err);
+ goto err_create;
+ }
+
+ memset(&dpbp_attr, 0, sizeof(struct dpbp_attr));
+ err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpbp->dpbp_handle,
+ &dpbp_attr);
+ if (err < 0) {
+ printf("dpbp_get_attributes() failed: %d\n", err);
+ goto err_get_attr;
}
- if (!strcmp(obj_desc.type, obj_type)) {
- debug("Discovered object: type %s, id %d, req %s\n",
- obj_desc.type, obj_desc.id, obj_type);
+ dflt_dpbp->dpbp_attr.id = dpbp_attr.id;
+#ifdef DEBUG
+ printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
+#endif
- error = dprc_init_container_obj(obj_desc, dprc_handle);
- if (error < 0) {
- printf("dprc_init_container_obj(i=%d) failed: %d\n",
- i, error);
- return error;
- }
+ err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+ if (err < 0) {
+ printf("dpbp_close() failed: %d\n", err);
+ goto err_close;
}
- return error;
+ return 0;
+
+err_close:
+ free(dflt_dpbp);
+err_get_attr:
+ dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+ dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+err_create:
+err_malloc:
+ return err;
}
-int fsl_mc_ldpaa_init(bd_t *bis)
+static int dpbp_exit(void)
{
- int i, error = 0;
- int dprc_opened = 0, container_id;
- int num_child_objects = 0;
+ int err;
- error = mc_init();
- if (error < 0)
- goto error;
+ err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id,
+ &dflt_dpbp->dpbp_handle);
+ if (err < 0) {
+ printf("dpbp_open() failed: %d\n", err);
+ goto err;
+ }
- error = dprc_get_container_id(dflt_mc_io, MC_CMD_NO_FLAGS,
- &container_id);
- if (error < 0) {
- printf("dprc_get_container_id() failed: %d\n", error);
- goto error;
+ err = dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpbp->dpbp_handle);
+ if (err < 0) {
+ printf("dpbp_destroy() failed: %d\n", err);
+ goto err;
}
- debug("fsl-mc: Container id=0x%x\n", container_id);
+#ifdef DEBUG
+ printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
+#endif
+
+ if (dflt_dpbp)
+ free(dflt_dpbp);
+ return 0;
- error = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, container_id,
- &dflt_dprc_handle);
- if (error < 0) {
- printf("dprc_open() failed: %d\n", error);
- goto error;
+err:
+ return err;
+}
+
+static int dpni_init(void)
+{
+ int err;
+ struct dpni_attr dpni_attr;
+ struct dpni_cfg dpni_cfg;
+
+ dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
+ if (!dflt_dpni) {
+ printf("No memory: malloc() failed\n");
+ err = -ENOMEM;
+ goto err_malloc;
}
- dprc_opened = true;
- error = dprc_get_obj_count(dflt_mc_io,
- MC_CMD_NO_FLAGS, dflt_dprc_handle,
- &num_child_objects);
- if (error < 0) {
- printf("dprc_get_obj_count() failed: %d\n", error);
- goto error;
+ memset(&dpni_cfg, 0, sizeof(dpni_cfg));
+ dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER |
+ DPNI_OPT_MULTICAST_FILTER;
+
+ err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg,
+ &dflt_dpni->dpni_handle);
+
+ if (err < 0) {
+ err = -ENODEV;
+ printf("dpni_create() failed: %d\n", err);
+ goto err_create;
}
- debug("Total child in container %d = %d\n", container_id,
- num_child_objects);
- if (num_child_objects != 0) {
- /*
- * Discover objects currently in the DPRC container in the MC:
- */
- for (i = 0; i < num_child_objects; i++)
- error = dprc_scan_container_obj(dflt_dprc_handle,
- "dpbp", i);
+ memset(&dpni_attr, 0, sizeof(struct dpni_attr));
+ err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ &dpni_attr);
+ if (err < 0) {
+ printf("dpni_get_attributes() failed: %d\n", err);
+ goto err_get_attr;
+ }
- for (i = 0; i < num_child_objects; i++)
- error = dprc_scan_container_obj(dflt_dprc_handle,
- "dpio", i);
+ dflt_dpni->dpni_id = dpni_attr.id;
+#ifdef DEBUG
+ printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+#endif
- for (i = 0; i < num_child_objects; i++)
- error = dprc_scan_container_obj(dflt_dprc_handle,
- "dpni", i);
+ err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ if (err < 0) {
+ printf("dpni_close() failed: %d\n", err);
+ goto err_close;
}
-error:
- if (dprc_opened)
- dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
- return error;
+ return 0;
+
+err_close:
+ free(dflt_dpni);
+err_get_attr:
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+err_create:
+err_malloc:
+ return err;
}
-void fsl_mc_ldpaa_exit(bd_t *bis)
+static int dpni_exit(void)
{
int err;
- if (get_mc_boot_status() == 0) {
- err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle);
- if (err < 0) {
- printf("dpio_disable() failed: %d\n", err);
- return;
- }
- err = dpio_reset(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle);
- if (err < 0) {
- printf("dpio_reset() failed: %d\n", err);
- return;
- }
- err = dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle);
- if (err < 0) {
- printf("dpio_close() failed: %d\n", err);
- return;
- }
+ err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id,
+ &dflt_dpni->dpni_handle);
+ if (err < 0) {
+ printf("dpni_open() failed: %d\n", err);
+ goto err;
+ }
- free(dflt_dpio);
- free(dflt_dpbp);
+ err = dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle);
+ if (err < 0) {
+ printf("dpni_destroy() failed: %d\n", err);
+ goto err;
}
- if (dflt_mc_io)
- free(dflt_mc_io);
+#ifdef DEBUG
+ printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+#endif
+
+ if (dflt_dpni)
+ free(dflt_dpni);
+ return 0;
+
+err:
+ return err;
+}
+
+static int mc_init_object(void)
+{
+ int err = 0;
+
+ err = dprc_init();
+ if (err < 0) {
+ printf("dprc_init() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpbp_init();
+ if (err < 0) {
+ printf("dpbp_init() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpio_init();
+ if (err < 0) {
+ printf("dpio_init() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpni_init();
+ if (err < 0) {
+ printf("dpni_init() failed: %d\n", err);
+ goto err;
+ }
+
+ return 0;
+err:
+ return err;
}
+
+int fsl_mc_ldpaa_exit(bd_t *bd)
+{
+ int err = 0;
+
+ if (bd && get_mc_boot_status() == -1)
+ return 0;
+
+ if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
+ printf("ERROR: fsl-mc: DPL is not applied\n");
+ err = -ENODEV;
+ return err;
+ }
+
+ if (bd && !get_mc_boot_status() && !get_dpl_apply_status())
+ return err;
+
+ err = dpbp_exit();
+ if (err < 0) {
+ printf("dpni_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpio_exit();
+ if (err < 0) {
+ printf("dpio_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpni_exit();
+ if (err < 0) {
+ printf("dpni_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dprc_exit();
+ if (err < 0) {
+ printf("dprc_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ return 0;
+err:
+ return err;
+}
+
+static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int err = 0;
+ if (argc < 3)
+ goto usage;
+
+ switch (argv[1][0]) {
+ case 's': {
+ char sub_cmd;
+ u64 mc_fw_addr, mc_dpc_addr;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+ u64 aiop_fw_addr;
+#endif
+
+ sub_cmd = argv[2][0];
+ switch (sub_cmd) {
+ case 'm':
+ if (argc < 5)
+ goto usage;
+
+ if (get_mc_boot_status() == 0) {
+ printf("fsl-mc: MC is already booted");
+ printf("\n");
+ return err;
+ }
+ mc_fw_addr = simple_strtoull(argv[3], NULL, 16);
+ mc_dpc_addr = simple_strtoull(argv[4], NULL,
+ 16);
+
+ if (!mc_init(mc_fw_addr, mc_dpc_addr))
+ err = mc_init_object();
+ break;
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+ case 'a':
+ if (argc < 4)
+ goto usage;
+ if (get_aiop_apply_status() == 0) {
+ printf("fsl-mc: AIOP FW is already");
+ printf(" applied\n");
+ return err;
+ }
+
+ aiop_fw_addr = simple_strtoull(argv[3], NULL,
+ 16);
+
+ err = load_mc_aiop_img(aiop_fw_addr);
+ if (!err)
+ printf("fsl-mc: AIOP FW applied\n");
+ break;
+#endif
+ default:
+ printf("Invalid option: %s\n", argv[2]);
+ goto usage;
+
+ break;
+ }
+ }
+ break;
+
+ case 'a': {
+ u64 mc_dpl_addr;
+
+ if (argc < 4)
+ goto usage;
+
+ if (get_dpl_apply_status() == 0) {
+ printf("fsl-mc: DPL already applied\n");
+ return err;
+ }
+
+ mc_dpl_addr = simple_strtoull(argv[3], NULL,
+ 16);
+
+ if (get_mc_boot_status() != 0) {
+ printf("fsl-mc: Deploying data path layout ..");
+ printf("ERROR (MC is not booted)\n");
+ return -ENODEV;
+ }
+
+ if (!fsl_mc_ldpaa_exit(NULL))
+ err = mc_apply_dpl(mc_dpl_addr);
+ break;
+ }
+ default:
+ printf("Invalid option: %s\n", argv[1]);
+ goto usage;
+ break;
+ }
+ return err;
+ usage:
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc,
+ "DPAA2 command to manage Management Complex (MC)",
+ "start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
+ "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
+ "fsl_mc start aiop [FW_addr] - Start AIOP\n"
+);
struct mc_command *cmd)
{
enum mc_cmd_status status;
- int timeout = 6000;
+ int timeout = 12000;
mc_write_command(mc_io->mmio_regs, cmd);
obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
-obj-$(CONFIG_LS2085A) += ls2085a.o
+obj-$(CONFIG_LS2080A) += ls2080a.o
+obj-$(CONFIG_LS2085A) += ls2080a.o
#include <hwconfig.h>
#include <phy.h>
#include <linux/compat.h>
+#include <fsl-mc/fsl_dpmac.h>
#include "ldpaa_eth.h"
return 0;
}
+#ifdef DEBUG
+static void ldpaa_eth_get_dpni_counter(void)
+{
+ int err = 0;
+ u64 value;
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_FRAME,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_FRAME failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_FRAME=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_BYTE,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_BYTE failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_BYTE=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_FRAME_DROP ,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DROP failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_FRAME_DROP =%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_FRAME_DISCARD,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DISCARD failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_FRAME_DISCARD=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_EGR_FRAME,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_EGR_FRAME failed\n");
+ return;
+ }
+ printf("DPNI_CNT_EGR_FRAME=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_EGR_BYTE ,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_EGR_BYTE failed\n");
+ return;
+ }
+ printf("DPNI_CNT_EGR_BYTE =%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_EGR_FRAME_DISCARD ,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_EGR_FRAME_DISCARD failed\n");
+ return;
+ }
+ printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value);
+}
+#endif
+
static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
const struct dpaa_fd *fd)
{
/* Read the frame annotation status word and check for errors */
fas = (struct ldpaa_fas *)
((uint8_t *)(fd_addr) +
- priv->buf_layout.private_data_size);
+ dflt_dpni->buf_layout.private_data_size);
status = le32_to_cpu(fas->status);
if (status & LDPAA_ETH_RX_ERR_MASK) {
printf("Rx frame error(s): 0x%08x\n",
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
struct dpni_queue_attr rx_queue_attr;
+ struct dpmac_link_state dpmac_link_state = { 0 };
+#ifdef DEBUG
+ struct dpni_link_state link_state;
+#endif
int err;
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
+ if (get_mc_boot_status() != 0) {
+ printf("ERROR (MC is not booted)\n");
+ return -ENODEV;
+ }
+
+ if (get_dpl_apply_status() == 0) {
+ printf("ERROR (DPL is deployed. No device available)\n");
+ return -ENODEV;
+ }
+ /* DPMAC initialization */
+ err = ldpaa_dpmac_setup(priv);
+ if (err < 0)
+ goto err_dpmac_setup;
+
+ /* DPMAC binding DPNI */
+ err = ldpaa_dpmac_bind(priv);
+ if (err)
+ goto err_dpamc_bind;
+
/* DPNI initialization */
err = ldpaa_dpni_setup(priv);
if (err < 0)
/* DPNI binding DPBP */
err = ldpaa_dpni_bind(priv);
if (err)
- goto err_bind;
+ goto err_dpni_bind;
err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, net_dev->enetaddr);
+ dflt_dpni->dpni_handle, net_dev->enetaddr);
if (err) {
printf("dpni_add_mac_addr() failed\n");
return err;
priv->phydev->duplex = DUPLEX_FULL;
#endif
- err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
printf("dpni_enable() failed\n");
return err;
}
+ dpmac_link_state.rate = SPEED_1000;
+ dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG;
+ dpmac_link_state.up = 1;
+ err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle, &dpmac_link_state);
+ if (err < 0) {
+ printf("dpmac_set_link_state() failed\n");
+ return err;
+ }
+
+#ifdef DEBUG
+ err = dpni_get_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, &link_state);
+ if (err < 0) {
+ printf("dpni_get_link_state() failed\n");
+ return err;
+ }
+
+ printf("link status: %d - ", link_state.up);
+ link_state.up == 0 ? printf("down\n") :
+ link_state.up == 1 ? printf("up\n") : printf("error state\n");
+#endif
+
/* TODO: support multiple Rx flows */
- err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
- 0, 0, &rx_queue_attr);
+ err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, 0, 0, &rx_queue_attr);
if (err) {
printf("dpni_get_rx_flow() failed\n");
goto err_rx_flow;
priv->rx_dflt_fqid = rx_queue_attr.fqid;
- err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
+ err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle,
&priv->tx_qdid);
if (err) {
printf("dpni_get_qdid() failed\n");
err_qdid:
err_rx_flow:
- dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
-err_bind:
+ dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+err_dpni_bind:
ldpaa_dpbp_free();
err_dpbp_setup:
- dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+err_dpamc_bind:
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_setup:
+err_dpmac_setup:
return err;
}
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
return;
+
+#ifdef DEBUG
+ ldpaa_eth_get_dpni_counter();
+#endif
+
+ err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle, &dpmac_endpoint);
+ if (err < 0)
+ printf("dprc_disconnect() failed dpmac_endpoint\n");
+
+ err = dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
+ if (err < 0)
+ printf("dpmac_destroy() failed\n");
+
/* Stop Tx and Rx traffic */
- err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0)
printf("dpni_disable() failed\n");
#endif
ldpaa_dpbp_free();
- dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
- dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
}
static void ldpaa_dpbp_drain_cnt(int count)
struct qbman_release_desc rd;
for (i = 0; i < 7; i++) {
- addr = memalign(L1_CACHE_BYTES, LDPAA_ETH_RX_BUFFER_SIZE);
+ addr = memalign(LDPAA_ETH_BUF_ALIGN, LDPAA_ETH_RX_BUFFER_SIZE);
if (!addr) {
printf("addr allocation failed\n");
goto err_alloc;
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
}
+static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv)
+{
+ int err = 0;
+ struct dpmac_cfg dpmac_cfg;
+
+ dpmac_cfg.mac_id = priv->dpmac_id;
+ err = dpmac_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpmac_cfg,
+ &priv->dpmac_handle);
+ if (err)
+ printf("dpmac_create() failed\n");
+ return err;
+}
+
+static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv)
+{
+ int err = 0;
+ struct dprc_connection_cfg dprc_connection_cfg = {
+ /* If both rates are zero the connection */
+ /* will be configured in "best effort" mode. */
+ .committed_rate = 0,
+ .max_rate = 0
+ };
+
+#ifdef DEBUG
+ struct dprc_endpoint dbg_endpoint;
+ int state = 0;
+#endif
+
+ memset(&dpmac_endpoint, 0, sizeof(struct dprc_endpoint));
+ sprintf(dpmac_endpoint.type, "dpmac");
+ dpmac_endpoint.id = priv->dpmac_id;
+
+ memset(&dpni_endpoint, 0, sizeof(struct dprc_endpoint));
+ sprintf(dpni_endpoint.type, "dpni");
+ dpni_endpoint.id = dflt_dpni->dpni_id;
+
+ err = dprc_connect(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle,
+ &dpmac_endpoint,
+ &dpni_endpoint,
+ &dprc_connection_cfg);
+ if (err)
+ printf("dprc_connect() failed\n");
+
+#ifdef DEBUG
+ err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle, &dpni_endpoint,
+ &dbg_endpoint, &state);
+ printf("%s, DPMAC Type= %s\n", __func__, dbg_endpoint.type);
+ printf("%s, DPMAC ID= %d\n", __func__, dbg_endpoint.id);
+ printf("%s, DPMAC State= %d\n", __func__, state);
+
+ memset(&dbg_endpoint, 0, sizeof(struct dprc_endpoint));
+ err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle, &dpmac_endpoint,
+ &dbg_endpoint, &state);
+ printf("%s, DPNI Type= %s\n", __func__, dbg_endpoint.type);
+ printf("%s, DPNI ID= %d\n", __func__, dbg_endpoint.id);
+ printf("%s, DPNI State= %d\n", __func__, state);
+#endif
+ return err;
+}
+
static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv)
{
int err;
/* and get a handle for the DPNI this interface is associate with */
- err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_id,
- &priv->dpni_handle);
+ err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id,
+ &dflt_dpni->dpni_handle);
if (err) {
printf("dpni_open() failed\n");
goto err_open;
}
err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->dpni_attrs);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->dpni_attrs);
if (err) {
printf("dpni_get_attributes() failed (err=%d)\n", err);
goto err_get_attr;
}
/* Configure our buffers' layout */
- priv->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
+ dflt_dpni->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
- DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
- priv->buf_layout.pass_parser_result = true;
- priv->buf_layout.pass_frame_status = true;
- priv->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE;
+ DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
+ DPNI_BUF_LAYOUT_OPT_DATA_ALIGN;
+ dflt_dpni->buf_layout.pass_parser_result = true;
+ dflt_dpni->buf_layout.pass_frame_status = true;
+ dflt_dpni->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE;
+ /* HW erratum mandates data alignment in multiples of 256 */
+ dflt_dpni->buf_layout.data_align = LDPAA_ETH_BUF_ALIGN;
/* ...rx, ... */
err = dpni_set_rx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->buf_layout);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout);
if (err) {
printf("dpni_set_rx_buffer_layout() failed");
goto err_buf_layout;
}
/* ... tx, ... */
- priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PARSER_RESULT;
+ /* remove Rx-only options */
+ dflt_dpni->buf_layout.options &= ~(DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
+ DPNI_BUF_LAYOUT_OPT_PARSER_RESULT);
err = dpni_set_tx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->buf_layout);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout);
if (err) {
printf("dpni_set_tx_buffer_layout() failed");
goto err_buf_layout;
}
/* ... tx-confirm. */
- priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
+ dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
err = dpni_set_tx_conf_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle,
- &priv->buf_layout);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout);
if (err) {
printf("dpni_set_tx_conf_buffer_layout() failed");
goto err_buf_layout;
* required tx data offset.
*/
err = dpni_get_tx_data_offset(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->tx_data_offset);
+ dflt_dpni->dpni_handle,
+ &priv->tx_data_offset);
if (err) {
printf("dpni_get_tx_data_offset() failed\n");
goto err_data_offset;
err_data_offset:
err_buf_layout:
err_get_attr:
- dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_open:
return err;
}
pools_params.num_dpbp = 1;
pools_params.pools[0].dpbp_id = (uint16_t)dflt_dpbp->dpbp_attr.id;
pools_params.pools[0].buffer_size = LDPAA_ETH_RX_BUFFER_SIZE;
- err = dpni_set_pools(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
- &pools_params);
+ err = dpni_set_pools(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, &pools_params);
if (err) {
printf("dpni_set_pools() failed\n");
return err;
dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR;
dflt_tx_flow.conf_err_cfg.use_default_queue = 0;
dflt_tx_flow.conf_err_cfg.errors_only = 1;
- err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
- &priv->tx_flow_id, &dflt_tx_flow);
+ err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, &priv->tx_flow_id,
+ &dflt_tx_flow);
if (err) {
printf("dpni_set_tx_flow() failed\n");
return err;
return 0;
}
-static int ldpaa_eth_netdev_init(struct eth_device *net_dev)
+static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
+ phy_interface_t enet_if)
{
int err;
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
- sprintf(net_dev->name, "DPNI%d", priv->dpni_id);
+ sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id,
+ phy_interface_strings[enet_if]);
net_dev->iobase = 0;
net_dev->init = ldpaa_eth_open;
return 0;
}
-int ldpaa_eth_init(struct dprc_obj_desc obj_desc)
+int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if)
{
struct eth_device *net_dev = NULL;
struct ldpaa_eth_priv *priv = NULL;
net_dev->priv = (void *)priv;
priv->net_dev = (struct eth_device *)net_dev;
- priv->dpni_id = obj_desc.id;
+ priv->dpmac_id = dpmac_id;
+ debug("%s dpmac_id=%d\n", __func__, dpmac_id);
- err = ldpaa_eth_netdev_init(net_dev);
+ err = ldpaa_eth_netdev_init(net_dev, enet_if);
if (err)
goto err_netdev_init;
#define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2)
#define LDPAA_ETH_RX_BUFFER_SIZE 2048
-/* Hardware requires alignment for ingress/egress buffer addresses
- * and ingress buffer lengths.
+/* Hardware requires alignment for buffer address and length: 256-byte
+ * for ingress, 64-byte for egress. Using 256 for both.
*/
-#define LDPAA_ETH_BUF_ALIGN 64
+#define LDPAA_ETH_BUF_ALIGN 256
/* So far we're only accomodating a skb backpointer in the frame's
* software annotation, but the hardware options are either 0 or 64.
struct ldpaa_eth_priv {
struct eth_device *net_dev;
- int dpni_id;
- uint16_t dpni_handle;
- struct dpni_attr dpni_attrs;
- /* Insofar as the MC is concerned, we're using one layout on all 3 types
- * of buffers (Rx, Tx, Tx-Conf).
- */
- struct dpni_buffer_layout buf_layout;
+ int dpmac_id;
+ uint16_t dpmac_handle;
+
uint16_t tx_data_offset;
uint32_t rx_dflt_fqid;
struct phy_device *phydev;
};
+struct dprc_endpoint dpmac_endpoint;
+struct dprc_endpoint dpni_endpoint;
+
extern struct fsl_mc_io *dflt_mc_io;
extern struct fsl_dpbp_obj *dflt_dpbp;
extern struct fsl_dpio_obj *dflt_dpio;
+extern struct fsl_dpni_obj *dflt_dpni;
+extern uint16_t dflt_dprc_handle;
static void ldpaa_dpbp_drain_cnt(int count);
static void ldpaa_dpbp_drain(void);
static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv);
static int ldpaa_dpbp_setup(void);
static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv);
+static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv);
+static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv);
#endif /* __LDPAA_H */
void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
{
phy_interface_t enet_if;
- int index = dpmac_id + sd * 8;
- dpmac_info[index].enabled = 0;
- dpmac_info[index].id = 0;
- dpmac_info[index].enet_if = PHY_INTERFACE_MODE_NONE;
+ dpmac_info[dpmac_id].enabled = 0;
+ dpmac_info[dpmac_id].id = 0;
+ dpmac_info[dpmac_id].phy_addr = -1;
+ dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE;
- enet_if = wriop_dpmac_enet_if(index, lane_prtcl);
+ enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
if (enet_if != PHY_INTERFACE_MODE_NONE) {
- dpmac_info[index].enabled = 1;
- dpmac_info[index].id = index;
- dpmac_info[index].enet_if = enet_if;
+ dpmac_info[dpmac_id].enabled = 1;
+ dpmac_info[dpmac_id].id = dpmac_id;
+ dpmac_info[dpmac_id].enet_if = enet_if;
}
}
wriop_dpmac_enable(dpmac_id);
}
+u8 wriop_is_enabled_dpmac(int dpmac_id)
+{
+ int i = wriop_dpmac_to_index(dpmac_id);
+
+ if (i == -1)
+ return -1;
+
+ return dpmac_info[i].enabled;
+}
+
+
void wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
{
int i = wriop_dpmac_to_index(dpmac_id);
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
};
+
+struct phy_driver aqr405_driver = {
+ .name = "Aquantia AQR405",
+ .uid = 0x3a1b4b2,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
int phy_aquantia_init(void)
{
phy_register(&aq1202_driver);
phy_register(&aq2104_driver);
phy_register(&aqr105_driver);
+ phy_register(&aqr405_driver);
return 0;
}
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
-#ifdef CONFIG_FSL_LAYERSCAPE
+#ifndef CONFIG_LS102XA
#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
-/* LUT registers */
-#define PCIE_LUT_BASE 0x80000
-#define PCIE_LUT_LCTRL0 0x7F8
-#define PCIE_LUT_DBG 0x7FC
-
#define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c
{
u32 state;
- state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
+ state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
LTSSM_STATE_MASK;
if (state < LTSSM_PCIE_L0) {
debug("....PCIe link error. LTSSM=0x%02x.\n", state);
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+#ifndef CONFIG_LS102XA
writel(PCIE_LCTRL0_VAL(pf, vf),
pcie->dbi + PCIE_LUT_BASE +
PCIE_LUT_LCTRL0);
+#endif
ls_pcie_ep_setup_bars(pcie->dbi);
ls_pcie_ep_setup_atu(pcie, info);
}
}
/* Disable CFG2 */
+#ifndef CONFIG_LS102XA
writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
+#endif
} else {
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
ls_pcie_ep_setup_atu(pcie, info);
}
#endif
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
void pcie_set_available_streamids(void *blob, const char *pcie_path,
u32 *stream_ids, int count)
reg &= 0x0000FFFF;
__raw_writel(reg, DI_STP_REP(disp, 6));
__raw_writel(0, DI_STP_REP(disp, 7));
- __raw_writel(0, DI_STP_REP(disp, 9));
+ __raw_writel(0, DI_STP_REP9(disp));
/* Init template microcode */
if (disp) {
#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9)
#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
- "fdt_high=0xcfffffff\0" \
- "initrd_high=0xcfffffff\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
- "fdt_high=0xcfffffff\0" \
- "initrd_high=0xcfffffff\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_H__
+#define __LS1043AQDS_H__
+
+#include "ls1043a_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x60100000
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS 0x51
+#define CONFIG_SYS_SPD_BUS_NUM 0
+
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
+#endif
+
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_SYS_HAS_SERDES
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHYLIB_10G
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+/* PHY address on QSGMII riser card on slot 1 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
+#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
+#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
+#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
+/* PHY address on QSGMII riser card on slot 2 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
+#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
+#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
+#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
+#endif
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1a) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0xe) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE 0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x7) | \
+ FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0xe) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+ FTIM2_NAND_TREH(0xa) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
+#endif
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE 0x7fb00000
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x44
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
+#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_NOR_MODE_AVD_NOR | \
+ CSOR_NOR_TRHZ_80)
+
+/*
+ * QIXIS Timing parameters for IFC GPCM
+ */
+#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
+ FTIM0_GPCM_TEADC(0x20) | \
+ FTIM0_GPCM_TEAHC(0x10))
+#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
+ FTIM2_GPCM_TCH(0x8) | \
+ FTIM2_GPCM_TWP(0xf0))
+#define CONFIG_SYS_FPGA_FTIM3 0x0
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_CH7301 0xC
+#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH7 0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_INA220
+/* The lowest and highest voltage allowed for LS1043AQDS */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (30 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_MII
+#define CONFIG_CMDLINE_TAG
+
+#endif /* __LS1043AQDS_H__ */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+#endif
+
/*
* Environment
*/
#define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
#endif /* __LS1043ARDB_H__ */
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH3
-#define CONFIG_LS2085A
#define CONFIG_MP
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974
-#include <asm/arch/ls2085a_stream_id.h>
+#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define CONFIG_SYS_HAS_SERDES
#define CPU_RELEASE_ADDR secondary_boot_func
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
/*
* DDR controller use 0 as the base address for binding.
#define CONFIG_SYS_DP_DDR_BASE_PHY 0
#define CONFIG_DP_DDR_CTRL 2
#define CONFIG_DP_DDR_NUM_CTRLS 1
+#endif
/* Generic Timer Definitions */
/*
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#ifdef CONFIG_LS2085A
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+#endif
/*
* Carve out a DDR region which will not be used by u-boot/Linux
#define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_PCIE4 /* PCIE controler 4 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#ifdef CONFIG_LS2080A
+#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
+#endif
+
+#ifdef CONFIG_LS2085A
#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
+#endif
#define CONFIG_SYS_PCI_64BIT
#define CONFIG_DISPLAY_CPUINFO
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
#ifndef __LS2_EMU_H
#define __LS2_EMU_H
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
+#ifdef CONFIG_LS2080A
+#define CONFIG_IDENT_STRING " LS2080A-EMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU"
+#endif
+
+#ifdef CONFIG_LS2085A
#define CONFIG_IDENT_STRING " LS2085A-EMU"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
+#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
#define CONFIG_FSL_DDR_SYNC_REFRESH
#ifndef __LS2_SIMU_H
#define __LS2_SIMU_H
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
+#ifdef CONFIG_LS2080A
+#define CONFIG_IDENT_STRING " LS2080A-SIMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU"
+#endif
+
+#ifdef CONFIG_LS2085A
#define CONFIG_IDENT_STRING " LS2085A-SIMU"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU"
+#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
/* SMSC 91C111 ethernet configuration */
#define CONFIG_SMC91111
#ifndef __LS2_QDS_H
#define __LS2_QDS_H
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
-
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
-
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
-#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL
/*
* I2C
#ifndef __LS2_RDB_H
#define __LS2_RDB_H
-#include "ls2085a_common.h"
+#include "ls2080a_common.h"
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
-
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
-
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
-#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL
/*
* I2C
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ * Luka Perkov <luka.perkov@sartura.hr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_NSA310S_H
+#define _CONFIG_NSA310S_H
+
+/* high level configuration options */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6192 1 /* SOC Name */
+#define CONFIG_KW88F6702 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/* add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
+
+/* compression configuration */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+
+/* commands configuration */
+#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* environment variables configuration */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0xe0000
+
+/* default environment variables */
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part root; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubifsload 0x800000 ${kernel}; " \
+ "ubifsload 0x700000 ${fdt}; " \
+ "ubifsumount; " \
+ "fdt addr 0x700000; fdt resize; fdt chosen; " \
+ "bootz 0x800000 - 0x700000"
+
+#define CONFIG_MTDPARTS \
+ "mtdparts=orion_nand:" \
+ "0xe0000@0x0(uboot)," \
+ "0x20000@0xe0000(uboot_env)," \
+ "0x100000@0x100000(second_stage_uboot)," \
+ "-@0x200000(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS \
+ "kernel=/boot/zImage\0" \
+ "fdt=/boot/nsa310s.dtb\0" \
+ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/* Ethernet driver configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 1
+#define CONFIG_PHY_GIGE
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/* SATA driver configuration */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/* RTC driver configuration */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NSA310S_H */
#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
#define __CONFIG_SOCFPGA_ARRIA5_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
#define CONFIG_DWMMC
#define CONFIG_SOCFPGA_DWMMC
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
#define __CONFIG_SOCFPGA_CYCLONE5_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
#ifndef __CONFIG_TERASIC_DE0_H__
#define __CONFIG_TERASIC_DE0_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
#ifndef __CONFIG_DENX_MCVEVK_H__
#define __CONFIG_DENX_MCVEVK_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_TERASIC_SOCKIT_H__
#define __CONFIG_TERASIC_SOCKIT_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_SOCRATES_H__
+#define __CONFIG_SOCFPGA_SOCRATES_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "EBV"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_socrates
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */
#ifndef _FLASH_H_
#define _FLASH_H_
-#ifndef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_SYS_MAX_FLASH_SECT
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#endif
+
/*-----------------------------------------------------------------------
* FLASH Info: contains chip specific data, per FLASH bank
*/
#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
-#endif /* !CONFIG_SYS_NO_FLASH */
-
#endif /* _FLASH_H_ */
/* Command IDs */
#define DPBP_CMDID_CLOSE 0x800
#define DPBP_CMDID_OPEN 0x804
+#define DPBP_CMDID_CREATE 0x904
+#define DPBP_CMDID_DESTROY 0x900
#define DPBP_CMDID_ENABLE 0x002
#define DPBP_CMDID_DISABLE 0x003
uint32_t cmd_flags,
uint16_t token);
+/**
+ * struct dpbp_cfg - Structure representing DPBP configuration
+ * @options: place holder
+ */
+struct dpbp_cfg {
+ uint32_t options;
+};
+
+/**
+ * dpbp_create() - Create the DPBP object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPBP object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpbp_open function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpbp_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpbp_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpbp_destroy() - Destroy the DPBP object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPBP object
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpbp_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
/**
* dpbp_enable() - Enable the DPBP.
* @mc_io: Pointer to MC portal's I/O object
/* Command IDs */
#define DPIO_CMDID_CLOSE 0x800
#define DPIO_CMDID_OPEN 0x803
+#define DPIO_CMDID_CREATE 0x903
+#define DPIO_CMDID_DESTROY 0x900
#define DPIO_CMDID_ENABLE 0x002
#define DPIO_CMDID_DISABLE 0x003
#define DPIO_CMD_OPEN(cmd, dpio_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id)
+/* cmd, param, offset, width, type, arg_name */
+#define DPIO_CMD_CREATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \
+ cfg->channel_mode);\
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\
+} while (0)
+
/* cmd, param, offset, width, type, arg_name */
#define DPIO_RSP_GET_ATTR(cmd, attr) \
do { \
DPIO_LOCAL_CHANNEL = 1,
};
+/**
+ * struct dpio_cfg - Structure representing DPIO configuration
+ * @channel_mode: Notification channel mode
+ * @num_priorities: Number of priorities for the notification channel (1-8);
+ * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
+ */
+struct dpio_cfg {
+ enum dpio_channel_mode channel_mode;
+ uint8_t num_priorities;
+};
+
+/**
+ * dpio_create() - Create the DPIO object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPIO object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpio_open() function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpio_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpio_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpio_destroy() - Destroy the DPIO object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPIO object
+ *
+ * Return: '0' on Success; Error code otherwise
+ */
+int dpio_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
/**
* dpio_enable() - Enable the DPIO, allow I/O portal operations.
* @mc_io: Pointer to MC portal's I/O object
--- /dev/null
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_DPMAC_H
+#define __FSL_DPMAC_H
+
+/* DPMAC Version */
+#define DPMAC_VER_MAJOR 3
+#define DPMAC_VER_MINOR 1
+
+/* Command IDs */
+#define DPMAC_CMDID_CLOSE 0x800
+#define DPMAC_CMDID_OPEN 0x80c
+#define DPMAC_CMDID_CREATE 0x90c
+#define DPMAC_CMDID_DESTROY 0x900
+
+#define DPMAC_CMDID_GET_ATTR 0x004
+#define DPMAC_CMDID_RESET 0x005
+
+#define DPMAC_CMDID_MDIO_READ 0x0c0
+#define DPMAC_CMDID_MDIO_WRITE 0x0c1
+#define DPMAC_CMDID_GET_LINK_CFG 0x0c2
+#define DPMAC_CMDID_SET_LINK_STATE 0x0c3
+#define DPMAC_CMDID_GET_COUNTER 0x0c4
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_CREATE(cmd, cfg) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_OPEN(cmd, dpmac_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\
+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
+ MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\
+ MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\
+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_MDIO_READ(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_MDIO_READ(cmd, data) \
+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \
+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \
+ MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_GET_COUNTER(cmd, type) \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_COUNTER(cmd, counter) \
+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
+
+/* Data Path MAC API
+ * Contains initialization APIs and runtime control APIs for DPMAC
+ */
+
+struct fsl_mc_io;
+
+/**
+ * dpmac_open() - Open a control session for the specified object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpmac_id: DPMAC unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpmac_create function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpmac_id,
+ uint16_t *token);
+
+/**
+ * dpmac_close() - Close the control session of the object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * enum dpmac_link_type - DPMAC link type
+ * @DPMAC_LINK_TYPE_NONE: No link
+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
+ */
+enum dpmac_link_type {
+ DPMAC_LINK_TYPE_NONE,
+ DPMAC_LINK_TYPE_FIXED,
+ DPMAC_LINK_TYPE_PHY,
+ DPMAC_LINK_TYPE_BACKPLANE
+};
+
+/**
+ * enum dpmac_eth_if - DPMAC Ethrnet interface
+ * @DPMAC_ETH_IF_MII: MII interface
+ * @DPMAC_ETH_IF_RMII: RMII interface
+ * @DPMAC_ETH_IF_SMII: SMII interface
+ * @DPMAC_ETH_IF_GMII: GMII interface
+ * @DPMAC_ETH_IF_RGMII: RGMII interface
+ * @DPMAC_ETH_IF_SGMII: SGMII interface
+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
+ * @DPMAC_ETH_IF_XAUI: XAUI interface
+ * @DPMAC_ETH_IF_XFI: XFI interface
+ */
+enum dpmac_eth_if {
+ DPMAC_ETH_IF_MII,
+ DPMAC_ETH_IF_RMII,
+ DPMAC_ETH_IF_SMII,
+ DPMAC_ETH_IF_GMII,
+ DPMAC_ETH_IF_RGMII,
+ DPMAC_ETH_IF_SGMII,
+ DPMAC_ETH_IF_QSGMII,
+ DPMAC_ETH_IF_XAUI,
+ DPMAC_ETH_IF_XFI
+};
+
+/**
+ * struct dpmac_cfg - Structure representing DPMAC configuration
+ * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP,
+ * the MAC IDs are continuous.
+ * For example: 2 WRIOPs, 16 MACs in each:
+ * MAC IDs for the 1st WRIOP: 1-16,
+ * MAC IDs for the 2nd WRIOP: 17-32.
+ */
+struct dpmac_cfg {
+ int mac_id;
+};
+
+/**
+ * dpmac_create() - Create the DPMAC object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPMAC object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpmac_open function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpmac_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpmac_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/* DPMAC IRQ Index and Events */
+
+/* IRQ index */
+#define DPMAC_IRQ_INDEX 0
+/* IRQ event - indicates a change in link state */
+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001
+/* irq event - Indicates that the link state changed */
+#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002
+
+/**
+ * struct dpmac_attr - Structure representing DPMAC attributes
+ * @id: DPMAC object ID
+ * @phy_id: PHY ID
+ * @link_type: link type
+ * @eth_if: Ethernet interface
+ * @max_rate: Maximum supported rate - in Mbps
+ * @version: DPMAC version
+ */
+struct dpmac_attr {
+ int id;
+ int phy_id;
+ enum dpmac_link_type link_type;
+ enum dpmac_eth_if eth_if;
+ uint32_t max_rate;
+ /**
+ * struct version - Structure representing DPMAC version
+ * @major: DPMAC major version
+ * @minor: DPMAC minor version
+ */
+ struct {
+ uint16_t major;
+ uint16_t minor;
+ } version;
+};
+
+/**
+ * dpmac_get_attributes - Retrieve DPMAC attributes.
+ *
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @attr: Returned object's attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_attr *attr);
+
+/**
+ * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters
+ * @phy_addr: MDIO device address
+ * @reg: Address of the register within the Clause 45 PHY device from which data
+ * is to be read
+ * @data: Data read/write from/to MDIO
+ */
+struct dpmac_mdio_cfg {
+ uint8_t phy_addr;
+ uint8_t reg;
+ uint16_t data;
+};
+
+/**
+ * dpmac_mdio_read() - Perform MDIO read transaction
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @cfg: Structure with MDIO transaction parameters
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_mdio_read(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg);
+
+/**
+ * dpmac_mdio_write() - Perform MDIO write transaction
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @cfg: Structure with MDIO transaction parameters
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_mdio_write(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg);
+
+/* DPMAC link configuration/state options */
+
+/* Enable auto-negotiation */
+#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL
+/* Enable half-duplex mode */
+#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
+/* Enable pause frames */
+#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL
+/* Enable a-symmetric pause frames */
+#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
+
+/**
+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
+ * @rate: Link's rate - in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ */
+struct dpmac_link_cfg {
+ uint32_t rate;
+ uint64_t options;
+};
+
+/**
+ * dpmac_get_link_cfg() - Get Ethernet link configuration
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @cfg: Returned structure with the link configuration
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_cfg *cfg);
+
+/**
+ * struct dpmac_link_state - DPMAC link configuration request
+ * @rate: Rate in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ * @up: Link state
+ */
+struct dpmac_link_state {
+ uint32_t rate;
+ uint64_t options;
+ int up;
+};
+
+/**
+ * dpmac_set_link_state() - Set the Ethernet link status
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @link_state: Link state configuration
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_state *link_state);
+
+/**
+ * enum dpni_counter - DPNI counter types
+ * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger
+ * (up to max frame length specified),
+ * good or bad.
+ * @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received
+ * with a wrong CRC
+ * @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length
+ * specified, with a bad frame check sequence.
+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors.
+ * Occurs when a receive FIFO overflows.
+ * Includes also packets truncated as a result of
+ * the receive FIFO overflow.
+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error
+ * (optional used for wrong SFD)
+ * @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64
+ * octets long with a good CRC.
+ * @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length
+ * specified, with a good frame check sequence.
+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC).
+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted
+ * (regular and PFC).
+ * @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid
+ * frames and valid pause frames.
+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame
+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame
+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received.
+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame
+ * @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error
+ * (except for undersized/fragment frame)
+ * @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid
+ * frames and valid pause frames transmitted.
+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame
+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame
+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame
+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error
+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including
+ * pause frames.
+ */
+enum dpmac_counter {
+ DPMAC_CNT_ING_FRAME_64,
+ DPMAC_CNT_ING_FRAME_127,
+ DPMAC_CNT_ING_FRAME_255,
+ DPMAC_CNT_ING_FRAME_511,
+ DPMAC_CNT_ING_FRAME_1023,
+ DPMAC_CNT_ING_FRAME_1518,
+ DPMAC_CNT_ING_FRAME_1519_MAX,
+ DPMAC_CNT_ING_FRAG,
+ DPMAC_CNT_ING_JABBER,
+ DPMAC_CNT_ING_FRAME_DISCARD,
+ DPMAC_CNT_ING_ALIGN_ERR,
+ DPMAC_CNT_EGR_UNDERSIZED,
+ DPMAC_CNT_ING_OVERSIZED,
+ DPMAC_CNT_ING_VALID_PAUSE_FRAME,
+ DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
+ DPMAC_CNT_ING_BYTE,
+ DPMAC_CNT_ING_MCAST_FRAME,
+ DPMAC_CNT_ING_BCAST_FRAME,
+ DPMAC_CNT_ING_ALL_FRAME,
+ DPMAC_CNT_ING_UCAST_FRAME,
+ DPMAC_CNT_ING_ERR_FRAME,
+ DPMAC_CNT_EGR_BYTE,
+ DPMAC_CNT_EGR_MCAST_FRAME,
+ DPMAC_CNT_EGR_BCAST_FRAME,
+ DPMAC_CNT_EGR_UCAST_FRAME,
+ DPMAC_CNT_EGR_ERR_FRAME,
+ DPMAC_CNT_ING_GOOD_FRAME
+};
+
+/**
+ * dpmac_get_counter() - Read a specific DPMAC counter
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @type: The requested counter
+ * @counter: Returned counter value
+ *
+ * Return: The requested counter; '0' otherwise.
+ */
+int dpmac_get_counter(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpmac_counter type,
+ uint64_t *counter);
+
+#endif /* __FSL_DPMAC_H */
/* Command IDs */
#define DPNI_CMDID_OPEN 0x801
#define DPNI_CMDID_CLOSE 0x800
+#define DPNI_CMDID_CREATE 0x901
+#define DPNI_CMDID_DESTROY 0x900
#define DPNI_CMDID_ENABLE 0x002
#define DPNI_CMDID_DISABLE 0x003
#define DPNI_CMD_OPEN(cmd, dpni_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_CREATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \
+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \
+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \
+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \
+ MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \
+ MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \
+ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \
+ MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \
+ MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \
+ MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \
+ MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \
+ MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \
+ MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \
+ MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \
+ MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \
+ MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \
+ MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \
+ MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \
+ MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \
+ MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \
+ cfg->adv.ipr_cfg.max_reass_frm_size); \
+ MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \
+ cfg->adv.ipr_cfg.min_frag_size_ipv4); \
+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \
+ cfg->adv.ipr_cfg.min_frag_size_ipv6); \
+ MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \
+ MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \
+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \
+ cfg->adv.ipr_cfg.max_open_frames_ipv4); \
+ MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \
+ cfg->adv.ipr_cfg.max_open_frames_ipv6); \
+} while (0)
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_SET_POOLS(cmd, cfg) \
uint32_t cmd_flags,
uint16_t token);
+/* DPNI configuration options */
+
+/**
+ * Allow different distribution key profiles for different traffic classes;
+ * if not set, a single key profile is assumed
+ */
+#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001
+
+/**
+ * Disable all non-error transmit confirmation; error frames are reported
+ * back to a common Tx error queue
+ */
+#define DPNI_OPT_TX_CONF_DISABLED 0x00000002
+
+/* Disable per-sender private Tx confirmation/error queue */
+#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004
+
+/**
+ * Support distribution based on hashed key;
+ * allows statistical distribution over receive queues in a traffic class
+ */
+#define DPNI_OPT_DIST_HASH 0x00000010
+
+/**
+ * Support distribution based on flow steering;
+ * allows explicit control of distribution over receive queues in a traffic
+ * class
+ */
+#define DPNI_OPT_DIST_FS 0x00000020
+
+/* Unicast filtering support */
+#define DPNI_OPT_UNICAST_FILTER 0x00000080
+/* Multicast filtering support */
+#define DPNI_OPT_MULTICAST_FILTER 0x00000100
+/* VLAN filtering support */
+#define DPNI_OPT_VLAN_FILTER 0x00000200
+/* Support IP reassembly on received packets */
+#define DPNI_OPT_IPR 0x00000800
+/* Support IP fragmentation on transmitted packets */
+#define DPNI_OPT_IPF 0x00001000
+/* VLAN manipulation support */
+#define DPNI_OPT_VLAN_MANIPULATION 0x00010000
+/* Support masking of QoS lookup keys */
+#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000
+/* Support masking of Flow Steering lookup keys */
+#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000
+
/**
* struct dpni_ipr_cfg - Structure representing IP reassembly configuration
* @max_reass_frm_size: Maximum size of the reassembled frame
uint16_t max_open_frames_ipv6;
};
+/**
+ * struct dpni_cfg - Structure representing DPNI configuration
+ * @mac_addr: Primary MAC address
+ * @adv: Advanced parameters; default is all zeros;
+ * use this structure to change default settings
+ */
+struct dpni_cfg {
+ uint8_t mac_addr[6];
+ /**
+ * struct adv - Advanced parameters
+ * @options: Mask of available options; use 'DPNI_OPT_<X>' values
+ * @start_hdr: Selects the packet starting header for parsing;
+ * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH'
+ * @max_senders: Maximum number of different senders; used as the number
+ * of dedicated Tx flows; Non-power-of-2 values are rounded
+ * up to the next power-of-2 value as hardware demands it;
+ * '0' will be treated as '1'
+ * @max_tcs: Maximum number of traffic classes (for both Tx and Rx);
+ * '0' will e treated as '1'
+ * @max_dist_per_tc: Maximum distribution size per Rx traffic class;
+ * Must be set to the required value minus 1;
+ * i.e. 0->1, 1->2, ... ,255->256;
+ * Non-power-of-2 values are rounded up to the next
+ * power-of-2 value as hardware demands it
+ * @max_unicast_filters: Maximum number of unicast filters;
+ * '0' is treated as '16'
+ * @max_multicast_filters: Maximum number of multicast filters;
+ * '0' is treated as '64'
+ * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in
+ * the QoS table; '0' is treated as '64'
+ * @max_qos_key_size: Maximum key size for the QoS look-up;
+ * '0' is treated as '24' which is enough for IPv4
+ * 5-tuple
+ * @max_dist_key_size: Maximum key size for the distribution;
+ * '0' is treated as '24' which is enough for IPv4 5-tuple
+ * @max_policers: Maximum number of policers;
+ * should be between '0' and max_tcs
+ * @max_congestion_ctrl: Maximum number of congestion control groups
+ * (CGs); covers early drop and congestion notification
+ * requirements for traffic classes;
+ * should be between '0' and max_tcs
+ * @ipr_cfg: IP reassembly configuration
+ */
+ struct {
+ uint32_t options;
+ enum net_prot start_hdr;
+ uint8_t max_senders;
+ uint8_t max_tcs;
+ uint8_t max_dist_per_tc[DPNI_MAX_TC];
+ uint8_t max_unicast_filters;
+ uint8_t max_multicast_filters;
+ uint8_t max_vlan_filters;
+ uint8_t max_qos_entries;
+ uint8_t max_qos_key_size;
+ uint8_t max_dist_key_size;
+ uint8_t max_policers;
+ uint8_t max_congestion_ctrl;
+ struct dpni_ipr_cfg ipr_cfg;
+ } adv;
+};
+
+/**
+ * dpni_create() - Create the DPNI object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPNI object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpni_open() function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpni_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpni_destroy() - Destroy the DPNI object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
/**
* struct dpni_pools_cfg - Structure representing buffer pools configuration
* @num_dpbp: Number of DPBPs
/* Command IDs */
#define DPRC_CMDID_CLOSE 0x800
#define DPRC_CMDID_OPEN 0x805
+#define DPRC_CMDID_CREATE 0x905
#define DPRC_CMDID_GET_ATTR 0x004
#define DPRC_CMDID_RESET_CONT 0x005
+#define DPRC_CMDID_CREATE_CONT 0x151
+#define DPRC_CMDID_DESTROY_CONT 0x152
#define DPRC_CMDID_GET_CONT_ID 0x830
#define DPRC_CMDID_GET_OBJ_COUNT 0x159
#define DPRC_CMDID_GET_OBJ 0x15A
#define DPRC_CMD_OPEN(cmd, container_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, container_id)
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \
+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \
+ MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\
+ MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\
+ MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\
+ MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\
+ MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\
+ MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\
+ MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\
+ MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\
+ MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\
+ MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\
+ MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\
+ MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\
+ MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\
+ MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\
+ MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\
+ MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\
+do { \
+ MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \
+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id)
+
/* cmd, param, offset, width, type, arg_name */
#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id)
char label[16];
};
+/**
+ * dprc_create_container() - Create child container
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPRC object
+ * @cfg: Child container configuration
+ * @child_container_id: Returned child container ID
+ * @child_portal_offset: Returned child portal offset from MC portal base
+ *
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dprc_create_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dprc_cfg *cfg,
+ int *child_container_id,
+ uint64_t *child_portal_offset);
+
+/**
+ * dprc_destroy_container() - Destroy child container.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPRC object
+ * @child_container_id: ID of the container to destroy
+ *
+ * This function terminates the child container, so following this call the
+ * child container ID becomes invalid.
+ *
+ * Notes:
+ * - All resources and objects of the destroyed container are returned to the
+ * parent container or destroyed if were created be the destroyed container.
+ * - This function destroy all the child containers of the specified
+ * container prior to destroying the container itself.
+ *
+ * warning: Only the parent container is allowed to destroy a child policy
+ * Container 0 can't be destroyed
+ *
+ * Return: '0' on Success; Error code otherwise.
+ *
+ */
+int dprc_destroy_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int child_container_id);
+
/**
* dprc_reset_container - Reset child container.
* @mc_io: Pointer to MC portal's I/O object
((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
(_portal_id) * SOC_MC_PORTAL_STRIDE))
+#define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \
+ ((_portal_offset) / SOC_MC_PORTAL_STRIDE)
+
struct mc_ccsr_registers {
u32 reg_gcr1;
u32 reserved1;
};
int get_mc_boot_status(void);
+int get_dpl_apply_status(void);
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+int get_aiop_apply_status(void);
+#endif
+u64 mc_get_dram_addr(void);
unsigned long mc_get_dram_block_size(void);
int fsl_mc_ldpaa_init(bd_t *bis);
-void fsl_mc_ldpaa_exit(bd_t *bis);
+int fsl_mc_ldpaa_exit(bd_t *bd);
#endif
#include <linux/compat.h>
#include <linux/types.h>
#include <linux/stringify.h>
+#include <phy.h>
#include <fsl-mc/fsl_mc_sys.h>
#include <fsl-mc/fsl_mc_cmd.h>
#include <fsl-mc/fsl_dprc.h>
#include <fsl-mc/fsl_dpbp.h>
+#include <fsl-mc/fsl_dpni.h>
extern struct fsl_mc_io *dflt_mc_io;
/**
* struct dpbp_node - DPBP strucuture
* @uint16_t handle: DPBP object handle
- * @int dpbp_id: DPBP id
+ * @struct dpbp_attr: DPBP attribute
*/
struct fsl_dpbp_obj {
uint16_t dpbp_handle;
*/
struct fsl_dpio_obj {
int dpio_id;
+ uint16_t dpio_handle;
struct qbman_swp *sw_portal; /** SW portal object */
};
extern struct fsl_dpio_obj *dflt_dpio;
-int mc_init(void);
-int ldpaa_eth_init(struct dprc_obj_desc obj_desc);
+/**
+ * struct dpni_node - DPNI strucuture
+ * @int dpni_id: DPNI id
+ * @uint16_t handle: DPNI object handle
+ * @struct dpni_attr: DPNI attributes
+ * @struct dpni_buffer_layout: DPNI buffer layout
+ */
+struct fsl_dpni_obj {
+ int dpni_id;
+ uint16_t dpni_handle;
+ struct dpni_attr dpni_attrs;
+ struct dpni_buffer_layout buf_layout;
+};
+
+extern struct fsl_dpni_obj *dflt_dpni;
+
+int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr);
+int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if);
+int mc_apply_dpl(u64 mc_dpl_addr);
#endif /* _FSL_MC_PRIVATE_H_ */
struct wriop_dpmac_info {
u8 enabled;
u8 id;
- u8 phy_addr;
u8 board_mux;
+ int phy_addr;
void *phy_regs;
phy_interface_t enet_if;
struct phy_device *phydev;
void wriop_init_dpmac(int, int, int);
void wriop_disable_dpmac(int);
void wriop_enable_dpmac(int);
+u8 wriop_is_enabled_dpmac(int dpmac_id);
void wriop_set_mdio(int, struct mii_dev *);
struct mii_dev *wriop_get_mdio(int);
void wriop_set_phy_address(int, int);
/* processor specific function */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step);
+void remove_unused_controllers(fsl_ddr_info_t *info);
/* board specific function */
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
#if defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
-#elif defined(CONFIG_LS2085A)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
- CONFIG_SYS_FSL_XHCI_USB2_ADDR}
+ CONFIG_SYS_FSL_XHCI_USB2_ADDR, \
+ CONFIG_SYS_FSL_XHCI_USB3_ADDR}
#endif /* _ASM_ARCH_XHCI_FSL_H_ */
main_hdr = image;
/* Fill in the main header */
- main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz;
- main_hdr->srcaddr = headersz;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz + sizeof(uint32_t) - headersz);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = has_ext;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
e = image_find_option(IMAGE_CFG_BOOT_FROM);
if (e)
main_hdr->nandeccmode = e->nandeccmode;
e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
if (e)
- main_hdr->nandpagesize = e->nandpagesz;
+ main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
int cfgi, datai;
ext_hdr = image + sizeof(struct main_hdr_v0);
- ext_hdr->offset = 0x40;
+ ext_hdr->offset = cpu_to_le32(0x40);
for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
e = &image_cfg[cfgi];
if (e->type != IMAGE_CFG_DATA)
continue;
- ext_hdr->rcfg[datai].raddr = e->regdata.raddr;
- ext_hdr->rcfg[datai].rdata = e->regdata.rdata;
+ ext_hdr->rcfg[datai].raddr =
+ cpu_to_le32(e->regdata.raddr);
+ ext_hdr->rcfg[datai].rdata =
+ cpu_to_le32(e->regdata.rdata);
datai++;
}
return 0;
}
- headersz += s.st_size +
- binarye->binary.nargs * sizeof(unsigned int);
+ headersz += sizeof(struct opt_hdr_v1) +
+ s.st_size +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t);
if (hasext)
*hasext = 1;
}
cur += sizeof(struct main_hdr_v1);
/* Fill the main header */
- main_hdr->blocksize = payloadsz - headersz + sizeof(uint32_t);
- main_hdr->headersz_lsb = headersz & 0xFFFF;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
+ main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
- main_hdr->srcaddr = headersz;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
main_hdr->version = 1;
e = image_find_option(IMAGE_CFG_BOOT_FROM);
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
struct opt_hdr_v1 *hdr = cur;
- unsigned int *args;
+ uint32_t *args;
size_t binhdrsz;
struct stat s;
int argi;
fstat(fileno(bin), &s);
binhdrsz = sizeof(struct opt_hdr_v1) +
- (binarye->binary.nargs + 1) * sizeof(unsigned int) +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t) +
s.st_size;
/*
* next-header byte and 3-byte alignment at the end.
*/
binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4;
- hdr->headersz_lsb = binhdrsz & 0xFFFF;
+ hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
cur += sizeof(struct opt_hdr_v1);
args = cur;
- *args = binarye->binary.nargs;
+ *args = cpu_to_le32(binarye->binary.nargs);
args++;
for (argi = 0; argi < binarye->binary.nargs; argi++)
- args[argi] = binarye->binary.args[argi];
+ args[argi] = cpu_to_le32(binarye->binary.args[argi]);
- cur += (binarye->binary.nargs + 1) * sizeof(unsigned int);
+ cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
ret = fread(cur, s.st_size, 1, bin);
if (ret != 1) {
free(image_cfg);
/* Build and add image checksum header */
- checksum = image_checksum32((uint32_t *)ptr, sbuf->st_size);
+ checksum =
+ cpu_to_le32(image_checksum32((uint32_t *)ptr, sbuf->st_size));
size = write(ifd, &checksum, sizeof(uint32_t));
if (size != sizeof(uint32_t)) {
fprintf(stderr, "Error:%s - Checksum write %d bytes %s\n",
tparams->header_size = alloc_len;
tparams->hdr = hdr;
- return 0;
+ /*
+ * The resulting image needs to be 4-byte aligned. At least
+ * the Marvell hdrparser tool complains if its unaligned.
+ * By returning 1 here in this function, called via
+ * tparams->vrec_header() in mkimage.c, mkimage will
+ * automatically pad the the resulting image to a 4-byte
+ * size if necessary.
+ */
+ return 1;
}
/*
#ifndef _KWBIMAGE_H_
#define _KWBIMAGE_H_
+#include <compiler.h>
#include <stdint.h>
#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
#define OPT_HDR_V1_REGISTER_TYPE 0x3
#define KWBHEADER_V1_SIZE(hdr) \
- (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
+ (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
enum kwbimage_cmd {
CMD_INVALID,
projects / karo-tx-uboot.git / commitdiff