drm/msm: Disable interrupts during init

Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 7250ffc6322fb70cc68e5c636f6fc6f087893023..1fa1fdda9ee2c5f2529aed1675a14ee48ea8a23e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -145,12 +145,16 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
                mutex_lock(&dev->struct_mutex);
                gpu->funcs->pm_resume(gpu);
                mutex_unlock(&dev->struct_mutex);
+
+               disable_irq(gpu->irq);
+
                ret = gpu->funcs->hw_init(gpu);
                if (ret) {
                        dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
                        gpu->funcs->destroy(gpu);
                        gpu = NULL;
                } else {
+                       enable_irq(gpu->irq);
                        /* give inactive pm a chance to kick in: */
                        msm_gpu_retire(gpu);
                }

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 6684ba8fa9be5825410e1504826c7539738d9acb..c3a4c53eb8b3a61a74ee22d74853923425beab10 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -129,11 +129,14 @@ void adreno_recover(struct msm_gpu *gpu)
        adreno_gpu->memptrs->wptr  = 0;
 
        gpu->funcs->pm_resume(gpu);
+
+       disable_irq(gpu->irq);
        ret = gpu->funcs->hw_init(gpu);
        if (ret) {
                dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
                /* hmm, oh well? */
        }
+       enable_irq(gpu->irq);
 }
 
 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,