ENGR00280101-2 [iMX6SL/iMX6DL] Add busfreq support

Change dtsi files to enable busfreq support.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 6a8e6a31eb1e672c9c88ff449809aa93450d3e84..fe4b1a31a1cc50d7d94215ec5b989c2de779667d 100644 (file)
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -61,7 +61,6 @@
                                "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
                        interrupts = <0 107 0x04>, <0 112 0x4>;
                        interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
-                       status = "disabled";
                        fsl,max_ddr_freq = <400000000>;
                };
 

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 4d6c765dc99f0c74cae1c9ff7348f602f4bb9fd4..f8cd3201d34263e2c75508c265afa3c541433409 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -94,6 +94,23 @@
                interrupt-parent = <&intc>;
                ranges;
 
+               busfreq { /* BUSFREQ */
+                       compatible = "fsl,imx6_busfreq";
+                       clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
+                                       <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
+                                       <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
+                                       <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2>,
+                                       <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
+                                       <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
+                                       <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM>,
+                                       <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
+                                       <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2>;
+                       clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
+                               "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
+                               "periph2_pre", "periph2_clk2_sel", "periph2_clk2";
+                       fsl,max_ddr_freq = <400000000>;
+               };
+
                L2: l2-cache@00a02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a02000 0x1000>;