regmap_read(afe->regmap, AFE_I2S_CON2, &val);
if (!!(val & AFE_I2S_CON2_EN) == enable)
- return; /* must skip soft reset */
-
- /* I2S soft reset begin */
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0x4);
+ return;
/* input */
regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
/* output */
regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
-
- /* I2S soft reset end */
- udelay(1);
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0);
}
static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
return 0;
mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
+ mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
return 0;
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
+ mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);
}
static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
mtk_afe_dais_set_clks(afe,
afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
NULL, 0);
+ mtk_afe_dais_set_clks(afe,
+ afe->clocks[MTK_CLK_I2S2_M], runtime->rate * 256,
+ NULL, 0);
/* config I2S */
ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
if (ret)