/*
- This is part of rtl8187 OpenSource driver.
-
Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
- Released under the terms of GPL (General Public Licence)
-
- Parts of this driver are based on the GPL part of the
- official realtek driver
-
- Parts of this driver are based on the rtl8192 driver skeleton
- from Patric Schenke & Andres Salomon
-
- Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
-
- We want to thank the Authors of those projects and the Ndiswrapper
- project Authors.
-*/
+ * This is part of rtl8187 OpenSource driver.
+
* Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
+ * Released under the terms of GPL (General Public Licence)
+ *
+ * Parts of this driver are based on the GPL part of the
+ * official realtek driver
+ *
+ * Parts of this driver are based on the rtl8192 driver skeleton
+ * from Patric Schenke & Andres Salomon
+ *
+ * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
+ *
+ * We want to thank the Authors of those projects and the Ndiswrapper
+ * project Authors.
+ */
#ifndef R819xU_H
#define R819xU_H
#include <linux/usb.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
-#include <linux/rtnetlink.h> //for rtnl_lock()
+#include <linux/rtnetlink.h>
#include <linux/wireless.h>
#include <linux/timer.h>
-#include <linux/proc_fs.h> // Necessary because we use the proc fs
+#include <linux/proc_fs.h>
#include <linux/if_arp.h>
#include <linux/random.h>
#include <asm/io.h>
#define RTL8192U
#define RTL819xU_MODULE_NAME "rtl819xU"
-//added for HW security, john.0629
+/* HW security */
#define FALSE 0
#define TRUE 1
#define MAX_KEY_LEN 61
#define BIT30 0x40000000
#define BIT31 0x80000000
-// Rx smooth factor
#define Rx_Smooth_Factor 20
#define DMESG(x,a...)
#define DMESGW(x,a...)
##args);\
}while(0);
-#define COMP_TRACE BIT0 // For function call tracing.
-#define COMP_DBG BIT1 // Only for temporary debug message.
-#define COMP_INIT BIT2 // during driver initialization / halt / reset.
-
-
-#define COMP_RECV BIT3 // Receive data path.
-#define COMP_SEND BIT4 // Send part path.
-#define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
-#define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
-#define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
-#define COMP_SWBW BIT8 // For bandwidth switch.
-#define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
-#define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
-#define COMP_QOS BIT11 // For QoS.
-#define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
-#define COMP_RM BIT13 // For Radio Measurement.
-#define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
-#define COMP_PHY BIT15
-#define COMP_CH BIT16 //channel setting debug
-#define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
-#define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
-#define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
-#define COMP_SEC BIT20 // Event handling
-#define COMP_LED BIT21 // For LED.
-#define COMP_RF BIT22 // For RF.
-//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
-#define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
-//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
-//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
-
-#define COMP_FIRMWARE BIT24 //for firmware downloading
-#define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
-#define COMP_AMSDU BIT26 // For A-MSDU Debugging
-
-#define COMP_SCAN BIT27
-#define COMP_DOWN BIT29 //for rm driver module
-#define COMP_RESET BIT30 //for silent reset
-#define COMP_ERR BIT31 //for error out, always on
+#define COMP_TRACE BIT0 /* Function call tracing. */
+#define COMP_DBG BIT1
+#define COMP_INIT BIT2 /* Driver initialization/halt/reset. */
+
+
+#define COMP_RECV BIT3 /* Receive data path. */
+#define COMP_SEND BIT4 /* Send data path. */
+#define COMP_IO BIT5
+/* 802.11 Power Save mode or System/Device Power state. */
+#define COMP_POWER BIT6
+/* 802.11 link related: join/start BSS, leave BSS. */
+#define COMP_EPROM BIT7
+#define COMP_SWBW BIT8 /* Bandwidth switch. */
+#define COMP_POWER_TRACKING BIT9 /* 8190 TX Power Tracking */
+#define COMP_TURBO BIT10 /* Turbo Mode */
+#define COMP_QOS BIT11
+#define COMP_RATE BIT12 /* Rate Adaptive mechanism */
+#define COMP_RM BIT13 /* Radio Measurement */
+#define COMP_DIG BIT14
+#define COMP_PHY BIT15
+#define COMP_CH BIT16 /* Channel setting debug */
+#define COMP_TXAGC BIT17 /* Tx power */
+#define COMP_HIPWR BIT18 /* High Power Mechanism */
+#define COMP_HALDM BIT19 /* HW Dynamic Mechanism */
+#define COMP_SEC BIT20 /* Event handling */
+#define COMP_LED BIT21
+#define COMP_RF BIT22
+#define COMP_RXDESC BIT23 /* Rx desc information for SD3 debug */
+
+/* 11n or 8190 specific code */
+
+#define COMP_FIRMWARE BIT24 /* Firmware downloading */
+#define COMP_HT BIT25 /* 802.11n HT related information */
+#define COMP_AMSDU BIT26 /* A-MSDU Debugging */
+#define COMP_SCAN BIT27
+#define COMP_DOWN BIT29 /* rm driver module */
+#define COMP_RESET BIT30 /* Silent reset */
+#define COMP_ERR BIT31 /* Error out, always on */
#define RTL819x_DEBUG
#ifdef RTL819x_DEBUG
printk("Assertion failed! %s,%s,%s,line=%d\n", \
#expr,__FILE__,__FUNCTION__,__LINE__); \
}
-//wb added to debug out data buf
-//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
+/*
+ * Debug out data buf.
+ * If you want to print DATA buffer related BA,
+ * please set ieee80211_debug_level to DATA|BA
+ */
#define RT_DEBUG_DATA(level, data, datalen) \
do{ if ((rt_global_debug_component & (level)) == (level)) \
{ \
#endif /* RTL8169_DEBUG */
-//
-// Queue Select Value in TxDesc
-//
+/* Queue Select Value in TxDesc */
#define QSLT_BK 0x1
#define QSLT_BE 0x0
#define QSLT_VI 0x4
#define IEEE80211_WATCH_DOG_TIME 2000
#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
-//for txpowertracking by amy
+/* For Tx Power Tracking */
#define OFDM_Table_Length 19
#define CCK_Table_length 12
-/* for rtl819x */
+/* For rtl819x */
typedef struct _tx_desc_819x_usb {
- //DWORD 0
+ /* DWORD 0 */
u16 PktSize;
u8 Offset;
u8 Reserved0:3;
u8 LINIP:1;
u8 OWN:1;
- //DWORD 1
+ /* DWORD 1 */
u8 TxFWInfoSize;
u8 RATid:3;
u8 DISFB:1;
u8 SecDescAssign:1;
u8 SecType:2;
- //DWORD 2
+ /* DWORD 2 */
u16 TxBufferSize;
u8 ResvForPaddingLen:7;
u8 Reserved3:1;
u8 Reserved4;
- //DWORD 3, 4, 5
+ /* DWORD 3, 4, 5 */
u32 Reserved5;
u32 Reserved6;
u32 Reserved7;
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
typedef struct _tx_desc_819x_usb_aggr_subframe {
- //DWORD 0
+ /* DWORD 0 */
u16 PktSize;
u8 Offset;
u8 TxFWInfoSize;
- //DWORD 1
+ /* DWORD 1 */
u8 RATid:3;
u8 DISFB:1;
u8 USERATE:1;
typedef struct _tx_desc_cmd_819x_usb {
- //DWORD 0
+ /* DWORD 0 */
u16 Reserved0;
u8 Reserved1;
u8 Reserved2:3;
u8 LINIP:1;
u8 OWN:1;
- //DOWRD 1
+ /* DOWRD 1 */
u8 TxFWInfoSize;
u8 Reserved3;
u8 QueueSelect;
u8 Reserved4;
- //DOWRD 2
+ /* DOWRD 2 */
u16 TxBufferSize;
u16 Reserved5;
- //DWORD 3,4,5
+ /* DWORD 3, 4, 5 */
u32 Reserved6;
u32 Reserved7;
u32 Reserved8;
typedef struct _tx_fwinfo_819x_usb {
- //DOWRD 0
- u8 TxRate:7;
- u8 CtsEnable:1;
- u8 RtsRate:7;
- u8 RtsEnable:1;
- u8 TxHT:1;
- u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
- u8 TxBandwidth:1; // This is used for HT MCS rate only.
- u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
- u8 STBC:2;
- u8 AllowAggregation:1;
- u8 RtsHT:1; //Interpret RtsRate field as high throughput data rate
- u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
- u8 RtsBandwidth:1; // This is used for HT MCS rate only.
- u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
- u8 RtsSTBC:2;
- u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
-
- //DWORD 1
- u32 RxMF:2;
- u32 RxAMD:3;
- u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
- u32 Reserved1:2;
- u32 TxAGCOffSet:4;
- u32 TxAGCSign:1;
- u32 Tx_INFO_RSVD:6;
- u32 PacketID:13;
+ /* DOWRD 0 */
+ u8 TxRate:7;
+ u8 CtsEnable:1;
+ u8 RtsRate:7;
+ u8 RtsEnable:1;
+ u8 TxHT:1;
+ u8 Short:1; /* Error out, always on */
+ u8 TxBandwidth:1; /* Used for HT MCS rate only */
+ u8 TxSubCarrier:2; /* Used for legacy OFDM rate only */
+ u8 STBC:2;
+ u8 AllowAggregation:1;
+ /* Interpret RtsRate field as high throughput data rate */
+ u8 RtsHT:1;
+ u8 RtsShort:1; /* Short PLCP for CCK or short GI for 11n MCS */
+ u8 RtsBandwidth:1; /* Used for HT MCS rate only */
+ u8 RtsSubcarrier:2;/* Used for legacy OFDM rate only */
+ u8 RtsSTBC:2;
+ /* Enable firmware to recalculate and assign packet duration */
+ u8 EnableCPUDur:1;
+
+ /* DWORD 1 */
+ u32 RxMF:2;
+ u32 RxAMD:3;
+ /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
+ u32 TxPerPktInfoFeedback:1;
+ u32 Reserved1:2;
+ u32 TxAGCOffSet:4;
+ u32 TxAGCSign:1;
+ u32 Tx_INFO_RSVD:6;
+ u32 PacketID:13;
}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
typedef struct rtl8192_rx_info {
}rtl8192_rx_info ;
typedef struct rx_desc_819x_usb{
- //DOWRD 0
+ /* DOWRD 0 */
u16 Length:14;
u16 CRC32:1;
u16 ICV:1;
u8 SWDec:1;
u8 Reserved1:4;
- //DWORD 1
+ /* DWORD 1 */
u32 Reserved2;
-
- //DWORD 2
-
- //DWORD 3
-
}rx_desc_819x_usb, *prx_desc_819x_usb;
#ifdef USB_RX_AGGREGATION_SUPPORT
typedef struct _rx_desc_819x_usb_aggr_subframe{
- //DOWRD 0
+ /* DOWRD 0 */
u16 Length:14;
u16 CRC32:1;
u16 ICV:1;
u8 Offset;
u8 RxDrvInfoSize;
- //DOWRD 1
+ /* DOWRD 1 */
u8 Shift:2;
u8 PHYStatus:1;
u8 SWDec:1;
u8 Reserved1:4;
u8 Reserved2;
u16 Reserved3;
- //DWORD 2
- //DWORD 3
}rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
#endif
typedef struct rx_drvinfo_819x_usb{
- //DWORD 0
+ /* DWORD 0 */
u16 Reserved1:12;
u16 PartAggr:1;
u16 FirstAGGR:1;
u8 Bcast:1;
u8 Reserved4:1;
- //DWORD 1
+ /* DWORD 1 */
u32 TSFL;
}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
-
-#define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
-#define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
+/* Support till 64 bit bus width OS */
+#define MAX_DEV_ADDR_SIZE 8
+/* For RTL8190 */
+#define MAX_FIRMWARE_INFORMATION_SIZE 32
#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
#define ENCRYPTION_MAX_OVERHEAD 128
#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
#endif
-#define scrclng 4 // octets for crc32 (FCS, ICV)
+/* Octets for crc32 (FCS, ICV) */
+#define scrclng 4
typedef enum rf_optype
{
typedef struct _rt_firmware{
firmware_status_e firmware_status;
u16 cmdpacket_frag_thresold;
-#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
+#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
u16 firmware_buf_size;
}rt_firmware, *prt_firmware;
-//+by amy 080507
-#define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
+/* Add this to 9100 bytes to receive A-MSDU from RT-AP */
+#define MAX_RECEIVE_BUFFER_SIZE 9100
typedef struct _rt_firmware_info_819xUsb{
u8 sz_info[16];
#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
-//=================================================================
-//=================================================================
+
+/*
+ * =================================================================
+ * =================================================================
+ */
#define EPROM_93c46 0
#define EPROM_93c56 1
u32 ht_mcs[4][16];
}rt_tx_rahis_t, *prt_tx_rahis_t;
typedef struct _RT_SMOOTH_DATA_4RF {
- char elements[4][100];//array to store values
- u32 index; //index to current array to store
- u32 TotalNum; //num of valid elements
- u32 TotalVal[4]; //sum of valid elements
+ char elements[4][100]; /* array to store values */
+ u32 index; /* index to current array to store */
+ u32 TotalNum; /* num of valid elements */
+ u32 TotalVal[4]; /* sum of valid elements */
}RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
-#define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
-//stats seems messed up, clean it ASAP
+/* This maybe changed for D-cut larger aggregation size */
+#define MAX_8192U_RX_SIZE 8192
+/* Stats seems messed up, clean it ASAP */
typedef struct Stats {
unsigned long txrdu;
unsigned long rxok;
unsigned long rxframgment;
unsigned long rxurberr;
unsigned long rxstaterr;
- unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
- unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
- unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
- unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
- unsigned long numpacket_matchbssid; // debug use only.
- unsigned long numpacket_toself; // debug use only.
- unsigned long num_process_phyinfo; // debug use only.
+ /* 0: Total, 1: OK, 2: CRC, 3: ICV */
+ unsigned long received_rate_histogram[4][32];
+ /* 0: Long preamble/GI, 1: Short preamble/GI */
+ unsigned long received_preamble_GI[2][32];
+ /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
+ unsigned long rx_AMPDUsize_histogram[5];
+ /* level: (<5), (5~10), (10~20), (20~40), (>40) */
+ unsigned long rx_AMPDUnum_histogram[5];
+ unsigned long numpacket_matchbssid;
+ unsigned long numpacket_toself;
+ unsigned long num_process_phyinfo;
unsigned long numqry_phystatus;
unsigned long numqry_phystatusCCK;
unsigned long numqry_phystatusHT;
- unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
+ /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
+ unsigned long received_bwtype[5];
unsigned long txnperr;
unsigned long txnpdrop;
unsigned long txresumed;
u8 last_packet_rate;
unsigned long slide_signal_strength[100];
unsigned long slide_evm[100];
- unsigned long slide_rssi_total; // For recording sliding window's RSSI value
- unsigned long slide_evm_total; // For recording sliding window's EVM value
- long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
+ /* For recording sliding window's RSSI value */
+ unsigned long slide_rssi_total;
+ /* For recording sliding window's EVM value */
+ unsigned long slide_evm_total;
+ /* Transformed in dbm. Beautified signal strength for UI, not correct */
+ long signal_strength;
long signal_quality;
long last_signal_strength_inpercent;
- long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
+ /* Correct smoothed ss in dbm, only used in driver
+ * to report real power now */
+ long recv_signal_power;
u8 rx_rssi_percentage[4];
u8 rx_evm_percentage[2];
long rxSNRdB[4];
rt_tx_rahis_t txrate;
- u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
- u32 Slide_Beacon_Total; //cosa add for beacon rssi
+ /* For beacon RSSI */
+ u32 Slide_Beacon_pwdb[100];
+ u32 Slide_Beacon_Total;
RT_SMOOTH_DATA_4RF cck_adc_pwdb;
u32 CurrentShowTxate;
} Stats;
-// Bandwidth Offset
+/* Bandwidth Offset */
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
-//+by amy 080507
typedef struct ChnlAccessSetting {
u16 SIFS_Timer;
}*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
typedef struct _BB_REGISTER_DEFINITION{
- u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
- u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
- u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
- u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
- u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
- u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
- u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
- u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
- u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
- u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
- u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
- u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
- u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
- u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
- u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
- u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
- u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
+ /* set software control: 0x870~0x877 [8 bytes] */
+ u32 rfintfs;
+ /* readback data: 0x8e0~0x8e7 [8 bytes] */
+ u32 rfintfi;
+ /* output data: 0x860~0x86f [16 bytes] */
+ u32 rfintfo;
+ /* output enable: 0x860~0x86f [16 bytes] */
+ u32 rfintfe;
+ /* LSSI data: 0x840~0x84f [16 bytes] */
+ u32 rf3wireOffset;
+ /* BB Band Select: 0x878~0x87f [8 bytes] */
+ u32 rfLSSI_Select;
+ /* Tx gain stage: 0x80c~0x80f [4 bytes] */
+ u32 rfTxGainStage;
+ /* wire parameter control1: 0x820~0x823, 0x828~0x82b,
+ * 0x830~0x833, 0x838~0x83b [16 bytes] */
+ u32 rfHSSIPara1;
+ /* wire parameter control2: 0x824~0x827, 0x82c~0x82f,
+ * 0x834~0x837, 0x83c~0x83f [16 bytes] */
+ u32 rfHSSIPara2;
+ /* Tx Rx antenna control: 0x858~0x85f [16 bytes] */
+ u32 rfSwitchControl;
+ /* AGC parameter control1: 0xc50~0xc53, 0xc58~0xc5b,
+ * 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
+ u32 rfAGCControl1;
+ /* AGC parameter control2: 0xc54~0xc57, 0xc5c~0xc5f,
+ * 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
+ u32 rfAGCControl2;
+ /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
+ * 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
+ u32 rfRxIQImbalance;
+ /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
+ * 0xc10~0xc13, 0xc18~0xc1b,
+ * 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
+ u32 rfRxAFE;
+ /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
+ * 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
+ u32 rfTxIQImbalance;
+ /* Tx IQ DC Offset and Tx DFIR type:
+ * 0xc84~0xc87, 0xc8c~0xc8f,
+ * 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
+ u32 rfTxAFE;
+ /* LSSI RF readback data: 0x8a0~0x8af [16 bytes] */
+ u32 rfLSSIReadBack;
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef enum _RT_RF_TYPE_819xU{
u32 low_rssi_threshold_ratr;
u32 low_rssi_threshold_ratr_40M;
u32 low_rssi_threshold_ratr_20M;
- u8 ping_rssi_enable; //cosa add for test
- u32 ping_rssi_ratr; //cosa add for test
- u32 ping_rssi_thresh_for_ra;//cosa add for test
+ u8 ping_rssi_enable;
+ u32 ping_rssi_ratr;
+ u32 ping_rssi_thresh_for_ra;
u32 last_ratr;
} rate_adaptive, *prate_adaptive;
} txbbgain_struct, *ptxbbgain_struct;
typedef struct _ccktxbbgain_struct {
- //The Value is from a22 to a29 one Byte one time is much Safer
+ /* The value is from a22 to a29, one byte one time is much safer */
u8 ccktxbb_valuearray[8];
} ccktxbbgain_struct,*pccktxbbgain_struct;
u8 cca;
} init_gain, *pinit_gain;
-//by amy 0606
typedef struct _phy_ofdm_rx_status_report_819xusb {
u8 trsw_gain_X[4];
}phy_sts_ofdm_819xusb_t;
typedef struct _phy_cck_rx_status_report_819xusb {
- /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
- 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
+ /* For CCK rate descriptor. This is an unsigned 8:1 variable.
+ * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
+ * Range from -64~+63.5. */
u8 adc_pwdb_X[4];
u8 sq_rpt;
u8 cck_agc_rpt;
RT_CID_819x_CAMEO = 6,
RT_CID_819x_RUNTOP = 7,
RT_CID_819x_Senao = 8,
- RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
+ RT_CID_TOSHIBA = 9,
RT_CID_819x_Netcore = 10,
RT_CID_Nettronix = 11,
RT_CID_DLINK = 12,
RT_CID_PRONET = 13,
}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
-//================================================================================
-// LED customization.
-//================================================================================
+/*
+ * ==========================================================================
+ * LED customization.
+ * ==========================================================================
+ */
typedef enum _LED_STRATEGY_8190{
- SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
- SW_LED_MODE1, // SW control for PCI Express
- SW_LED_MODE2, // SW control for Cameo.
- SW_LED_MODE3, // SW contorl for RunTop.
- SW_LED_MODE4, // SW control for Netcore
- HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
+ SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
+ SW_LED_MODE1, /* SW control for PCI Express */
+ SW_LED_MODE2, /* SW control for Cameo. */
+ SW_LED_MODE3, /* SW control for RunTop. */
+ SW_LED_MODE4, /* SW control for Netcore. */
+ /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
+ HW_LED,
}LED_STRATEGY_8190, *PLED_STRATEGY_8190;
typedef enum _RESET_TYPE {
typedef struct r8192_priv {
struct usb_device *udev;
- //added for maintain info from eeprom
+ /* For maintain info from eeprom */
short epromtype;
u16 eeprom_vid;
u16 eeprom_pid;
int irq;
struct ieee80211_device *ieee80211;
- short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
- u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
+ /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
+ short card_8192;
+ /* If TCR reports card V B/C, this discriminates */
+ u8 card_8192_version;
short enable_gpio0;
enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
short hw_plcp_len;
short up;
- short crcmon; //if 1 allow bad crc frame reception in monitor mode
+ /* If 1, allow bad crc frame, reception in monitor mode */
+ short crcmon;
struct semaphore wx_sem;
- struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
+ struct semaphore rf_sem; /* Used to lock rf write operation */
- u8 rf_type; //0 means 1T2R, 1 means 2T4R
+ u8 rf_type; /* 0: 1T2R, 1: 2T4R */
RT_RF_TYPE_819xU rf_chip;
short (*rf_set_sens)(struct net_device *dev,short sens);
void (*rf_close)(struct net_device *dev);
void (*rf_init)(struct net_device *dev);
short promisc;
- /*stats*/
+ /* Stats */
struct Stats stats;
struct iw_statistics wstats;
- /*RX stuff*/
+ /* RX stuff */
struct urb **rx_urb;
struct urb **rx_cmd_urb;
#ifdef THOMAS_BEACON
u32 *oldaddr;
#endif
#ifdef THOMAS_TASKLET
- atomic_t irt_counter;//count for irq_rx_tasklet
+ atomic_t irt_counter; /* count for irq_rx_tasklet */
#endif
#ifdef JACKSON_NEW_RX
struct sk_buff **pp_rxskb;
int rx_inx;
#endif
-/* modified by davad for Rx process */
struct sk_buff_head rx_queue;
struct sk_buff_head skb_queue;
struct work_struct qos_activate;
short tx_urb_index;
- atomic_t tx_pending[0x10];//UART_PRIORITY+1
+ atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
struct tasklet_struct irq_rx_tasklet;
struct urb *rxurb_task;
- //2 Tx Related variables
+ /* Tx Related variables */
u16 ShortRetryLimit;
u16 LongRetryLimit;
u32 TransmitConfig;
- u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
+ u8 RegCWinMin; /* For turbo mode CW adaptive */
u32 LastRxDescTSFHigh;
u32 LastRxDescTSFLow;
- //2 Rx Related variables
+ /* Rx Related variables */
u16 EarlyRxThreshold;
u32 ReceiveConfig;
u8 AcmControl;
struct work_struct reset_wq;
/**********************************************************/
- //for rtl819xUsb
+ /* For rtl819xUsb */
u16 basic_rate;
u8 short_preamble;
u8 slot_time;
bool bDcut;
bool bCurrentRxAggrEnable;
- u8 Rf_Mode; //add for Firmware RF -R/W switch
+ u8 Rf_Mode; /* For Firmware RF -R/W switch */
prt_firmware pFirmware;
rtl819xUsb_loopback_e LoopbackMode;
u16 EEPROMTxPowerDiff;
u8 EEPROMPwDiff;
u8 EEPROMCrystalCap;
u8 EEPROM_Def_Ver;
- u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
+ u8 EEPROMTxPowerLevelCCK; /* CCK channel 1~14 */
u8 EEPROMTxPowerLevelCCK_V1[3];
- u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
- u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
+ u8 EEPROMTxPowerLevelOFDM24G[3]; /* OFDM 2.4G channel 1~14 */
+ u8 EEPROMTxPowerLevelOFDM5G[24]; /* OFDM 5G */
-/*PHY related*/
- BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
- // Read/write are allow for following hardware information variables
+ /* PHY related */
+ BB_REGISTER_DEFINITION_T PHYRegDef[4]; /* Radio A/B/C/D */
+ /* Read/write are allow for following hardware information variables */
u32 MCSTxPowerLevelOriginalOffset[6];
u32 CCKTxPowerLevelOriginalOffset;
- u8 TxPowerLevelCCK[14]; // CCK channel 1~14
- u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
- u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
+ u8 TxPowerLevelCCK[14]; /* CCK channel 1~14 */
+ u8 TxPowerLevelOFDM24G[14]; /* OFDM 2.4G channel 1~14 */
+ u8 TxPowerLevelOFDM5G[14]; /* OFDM 5G */
u32 Pwr_Track;
u8 TxPowerDiff;
- u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
- u8 CrystalCap; // CrystalCap.
- u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
+ u8 AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
+ u8 CrystalCap;
+ u8 ThermalMeter[2]; /* index 0: RFIC0, index 1: RFIC1 */
u8 CckPwEnl;
- // Use to calculate PWBD.
+ /* Use to calculate PWBD */
u8 bCckHighPower;
long undecorated_smoothed_pwdb;
- //for set channel
+ /* For set channel */
u8 SwChnlInProgress;
u8 SwChnlStage;
u8 SwChnlStep;
u8 SetBWModeInProgress;
HT_CHANNEL_WIDTH CurrentChannelBW;
u8 ChannelPlan;
- // 8190 40MHz mode
- //
- u8 nCur40MhzPrimeSC; // Control channel sub-carrier
- // Joseph test for shorten RF configuration time.
- // We save RF reg0 in this variable to reduce RF reading.
- //
+ /* 8190 40MHz mode */
+ /* Control channel sub-carrier */
+ u8 nCur40MhzPrimeSC;
+ /* Test for shorten RF configuration time.
+ * We save RF reg0 in this variable to reduce RF reading. */
u32 RfReg0Value[4];
u8 NumTotalRFPath;
bool brfpath_rxenable[4];
- //RF set related
+ /* RF set related */
bool SetRFPowerStateInProgress;
-//+by amy 080507
struct timer_list watch_dog_timer;
-//+by amy 080515 for dynamic mechenism
- //Add by amy Tx Power Control for Near/Far Range 2008/05/15
- bool bdynamic_txpower; //bDynamicTxPower
- bool bDynamicTxHighPower; // Tx high power state
- bool bDynamicTxLowPower; // Tx low power state
+ /* For dynamic mechanism */
+ /* Tx Power Control for Near/Far Range */
+ bool bdynamic_txpower;
+ bool bDynamicTxHighPower;
+ bool bDynamicTxLowPower;
bool bLastDTPFlag_High;
bool bLastDTPFlag_Low;
bool bstore_last_dtpflag;
- bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
- //Add by amy for Rate Adaptive
+ /* Define to discriminate on High power State or
+ * on sitesurvey to change Tx gain index */
+ bool bstart_txctrl_bydtp;
rate_adaptive rate_adaptive;
- //Add by amy for TX power tracking
- //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
- txbbgain_struct txbbgain_table[TxBBGainTableLength];
- u8 txpower_count;//For 6 sec do tracking again
- bool btxpower_trackingInit;
- u8 OFDM_index;
- u8 CCK_index;
- //2007/09/10 Mars Add CCK TX Power Tracking
+ /* TX power tracking
+ * OPEN/CLOSE TX POWER TRACKING */
+ txbbgain_struct txbbgain_table[TxBBGainTableLength];
+ u8 txpower_count; /* For 6 sec do tracking again */
+ bool btxpower_trackingInit;
+ u8 OFDM_index;
+ u8 CCK_index;
+ /* CCK TX Power Tracking */
ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
u8 rfa_txpowertrackingindex;
bool bcck_in_ch14;
bool btxpowerdata_readfromEEPORM;
u16 TSSI_13dBm;
- //For Backup Initial Gain
init_gain initgain_backup;
u8 DefaultInitialGain[4];
- // For EDCA Turbo mode, Added by amy 080515.
+ /* For EDCA Turbo mode */
bool bis_any_nonbepkts;
bool bcurrent_turbo_EDCA;
bool bis_cur_rdlstate;
struct timer_list fsync_timer;
- bool bfsync_processing; // 500ms Fsync timer is active or not
+ bool bfsync_processing; /* 500ms Fsync timer is active or not */
u32 rate_record;
u32 rateCountDiffRecord;
u32 ContinueDiffCount;
u8 framesync;
u32 framesyncC34;
u8 framesyncMonitor;
- //Added by amy 080516 for RX related
u16 nrxAMPDU_size;
u8 nrxAMPDU_aggr_num;
- //by amy for gpio
+ /* For gpio */
bool bHwRadioOff;
- //by amy for reset_count
u32 reset_count;
bool bpbc_pressed;
- //by amy for debug
u32 txpower_checkcnt;
u32 txpower_tracking_callback_cnt;
u8 thermal_read_val[40];
u32 ccktxpower_adjustcnt_ch14;
u8 tx_fwinfo_force_subcarriermode;
u8 tx_fwinfo_force_subcarrierval;
- //by amy for silent reset
+ /* For silent reset */
RESET_TYPE ResetProgress;
bool bForcedSilentReset;
bool bDisableNormalResetCheck;
u16 SifsTime;
- //define work item by amy 080526
+ /* Define work item */
struct delayed_work update_beacon_wq;
struct delayed_work watch_dog_wq;
struct workqueue_struct *priv_wq;
}r8192_priv;
-//for rtl8187B
+/* For rtl8187B */
typedef enum{
BULK_PRIORITY = 0x01,
LOW_PRIORITY,
NORM_PRIORITY,
VO_PRIORITY,
- VI_PRIORITY, //0x05
+ VI_PRIORITY,
BE_PRIORITY,
BK_PRIORITY,
RSVD2,
RSVD3,
- BEACON_PRIORITY, //0x0A
+ BEACON_PRIORITY,
HIGH_PRIORITY,
MANAGE_PRIORITY,
RSVD4,
RSVD5,
- UART_PRIORITY //0x0F
+ UART_PRIORITY
} priority_t;
typedef enum{
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