When exiting from LPAPM mode, ARM clock is run at 266.67MHZ for
a few instructions while the voltage is still at 0.85V.
Fix this issue by setting the ARM-PODF divider before
switching the parent.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
__raw_writel(0x02, MXC_CCM_CACRR);
clk_set_rate(pll1, cpu_op_tbl[0].pll_rate);
- clk_set_parent(pll1_sw_clk, pll1);
- /* Set the divider to ARM_PODF to 5. */
+ /* Set the divider to ARM_PODF to 5 before
+ * switching the parent.
+ */
__raw_writel(0x4, MXC_CCM_CACRR);
+ clk_set_parent(pll1_sw_clk, pll1);
}
if (!completion_done(&voltage_change_cmpl))