ENGR00176974 MX6Q: make 624M WP work, change 624 WP to 672 WP

since pll1 have a limit that cannot scaling down to 650M and below
so change the 600M WP to 672MHz.

otherwise, the 600WP's clock will depens on last frequency.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>

diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c
index 088a9fde273894dadce49854bd6006fd21624245..4fe3086dd7ccc50471ddd21290daf818669a060e 100644 (file)
--- a/arch/arm/mach-mx6/cpu_op-mx6.c
+++ b/arch/arm/mach-mx6/cpu_op-mx6.c
@@ -36,8 +36,8 @@ static struct cpu_op mx6_cpu_op_1_2G[] = {
         .cpu_podf = 0,
         .cpu_voltage = 1100000,},
        {
-        .pll_rate = 624000000,
-        .cpu_rate = 624000000,
+        .pll_rate = 672000000,
+        .cpu_rate = 672000000,
         .cpu_voltage = 1100000,},
         {
          .pll_rate = 792000000,
@@ -64,8 +64,8 @@ static struct cpu_op mx6_cpu_op_1G[] = {
         .cpu_podf = 0,
         .cpu_voltage = 1100000,},
        {
-        .pll_rate = 624000000,
-        .cpu_rate = 624000000,
+        .pll_rate = 672000000,
+        .cpu_rate = 672000000,
         .cpu_voltage = 1100000,},
         {
          .pll_rate = 792000000,