cciss: add half second delay to PCI PM reset code

After using PCI Power Management to reset the Smart Array in kdump kernels
we need some delay.  Otherwise we may think the board failed to reset and
bail out.  This affects all users with a Smart Array P600.

Signed-off-by: Mike Miller <mike.miller@hp.com>
Cc: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Andrew Morton <akpm@google.com>

diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index 6da7edea700a274815fb4367598478197a853f4e..461d82f6cd1036677fdf32b2a20f72f6cdc1fa2e 100644 (file)
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -4550,13 +4550,13 @@ static int cciss_controller_hard_reset(struct pci_dev *pdev,
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
                pmcsr |= PCI_D3hot;
                pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
-
                msleep(500);
 
                /* enter the D0 power management state */
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
                pmcsr |= PCI_D0;
                pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
+               msleep(500);
        }
        return 0;
 }