ENGR00226096 mx6sl: remove high set point for usdhc

- Due to usdhc ADMA mode has issue working with low bus freq, in
driver usdhc has been configured to SDMA mode already. So it is
not necessary to keep high set point flag any more.

Signed-off-by: Ryan QIAN <b32804@freescale.com>
Acked-by: Dong Aisheng <b29396@freescale.com>
Acked-by: Robby CAI <r63905@freescale.com>

diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 616099180008962abf67d0bd176eb61819f7df2b..b340c9e3ed6b5893937b44ff80af346c4dff3061 100755 (executable)
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -2098,7 +2098,6 @@ static struct clk usdhc1_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc1_set_rate,
        .get_rate = _clk_usdhc1_get_rate,
-       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
@@ -2156,7 +2155,6 @@ static struct clk usdhc2_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc2_set_rate,
        .get_rate = _clk_usdhc2_get_rate,
-       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
@@ -2215,7 +2213,6 @@ static struct clk usdhc3_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc3_set_rate,
        .get_rate = _clk_usdhc3_get_rate,
-       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
@@ -2274,7 +2271,6 @@ static struct clk usdhc4_clk = {
        .round_rate = _clk_usdhc_round_rate,
        .set_rate = _clk_usdhc4_set_rate,
        .get_rate = _clk_usdhc4_get_rate,
-       .flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi_round_rate(struct clk *clk,