ENGR00180075 MX6: change CLKO source to pll4_audio_main_clk

change CLKO source to pll4_audio_main_clk for low power
mode consideration

Signed-off-by: Gary Zhang <b13634@freescale.com>

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 3b815fe0e5bd4dd9f9b702c93ae311776110c966..20cfc5511c30d24e63e23e6777fc7006806bb7d4 100644 (file)
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -5180,8 +5180,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
        sata_clk[0].disable(&sata_clk[0]);
        pcie_clk[0].disable(&pcie_clk[0]);
 
-       /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
-       clk_set_rate(&pll4_audio_main_clk, 650000000);
+       /* Initialize Audio and Video PLLs to valid frequency. */
+       clk_set_rate(&pll4_audio_main_clk, 176000000);
        clk_set_rate(&pll5_video_main_clk, 650000000);
 
        clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
@@ -5226,7 +5226,7 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
        clk_set_parent(&clko2_clk, &osc_clk);
        clk_set_rate(&clko2_clk, 2400000);
 
-       clk_set_parent(&clko_clk, &ipg_clk);
+       clk_set_parent(&clko_clk, &pll4_audio_main_clk);
        /*
         * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
         * rate convertion and this clock frequency can not be too high, set