]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
Merge tag 'drm-intel-fixes-2017-05-18-1' of git://anongit.freedesktop.org/git/drm...
authorDave Airlie <airlied@redhat.com>
Fri, 19 May 2017 00:23:14 +0000 (10:23 +1000)
committerDave Airlie <airlied@redhat.com>
Fri, 19 May 2017 00:23:14 +0000 (10:23 +1000)
drm/i915 fixes for v4.12-rc2

* tag 'drm-intel-fixes-2017-05-18-1' of git://anongit.freedesktop.org/git/drm-intel:
  drm/i915: don't do allocate_va_range again on PIN_UPDATE
  drm/i915: Fix rawclk readout for g4x
  drm/i915: Fix runtime PM for LPE audio
  drm/i915/glk: Fix DSI "*ERROR* ULPS is still active" messages
  drm/i915/gvt: avoid unnecessary vgpu switch
  drm/i915/gvt: not to restore in-context mmio
  drm/i915/gvt: fix typo: "supporte" -> "support"

drivers/gpu/drm/i915/gvt/handlers.c
drivers/gpu/drm/i915/gvt/render.c
drivers/gpu/drm/i915/gvt/sched_policy.c
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_cdclk.c
drivers/gpu/drm/i915/intel_dsi.c
drivers/gpu/drm/i915/intel_lpe_audio.c
sound/x86/intel_hdmi_audio.c

index 0ad1a508e2af478dc9fb91df18bdc95304efad44..c995e540ff96e1f8a18a9232de2b26794fa03aa2 100644 (file)
@@ -1244,7 +1244,7 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
        mode = vgpu_vreg(vgpu, offset);
 
        if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
-               WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n",
+               WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
                                vgpu->id);
                return 0;
        }
index c6e7972ac21da8eda7143619a401554e2575a160..a5e11d89df2f86d13dc546f7b3e1a9e9c8ba7d97 100644 (file)
@@ -340,6 +340,9 @@ void intel_gvt_restore_render_mmio(struct intel_vgpu *vgpu, int ring_id)
                } else
                        v = mmio->value;
 
+               if (mmio->in_context)
+                       continue;
+
                I915_WRITE(mmio->reg, v);
                POSTING_READ(mmio->reg);
 
index 79ba4b3440aafd9537f287028d1e23a6186109a1..f25ff133865f1327936483ac166b97c41e0baa60 100644 (file)
@@ -129,9 +129,13 @@ static void try_to_schedule_next_vgpu(struct intel_gvt *gvt)
        struct vgpu_sched_data *vgpu_data;
        ktime_t cur_time;
 
-       /* no target to schedule */
-       if (!scheduler->next_vgpu)
+       /* no need to schedule if next_vgpu is the same with current_vgpu,
+        * let scheduler chose next_vgpu again by setting it to NULL.
+        */
+       if (scheduler->next_vgpu == scheduler->current_vgpu) {
+               scheduler->next_vgpu = NULL;
                return;
+       }
 
        /*
         * after the flag is set, workload dispatch thread will
index 2aa6b97fd22f28436b984a6ae9a537f36ada545a..a0563e18d753fd84731f8372efc7a938d2898a6b 100644 (file)
@@ -195,9 +195,12 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
        u32 pte_flags;
        int ret;
 
-       ret = vma->vm->allocate_va_range(vma->vm, vma->node.start, vma->size);
-       if (ret)
-               return ret;
+       if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
+               ret = vma->vm->allocate_va_range(vma->vm, vma->node.start,
+                                                vma->size);
+               if (ret)
+                       return ret;
+       }
 
        vma->pages = vma->obj->mm.pages;
 
@@ -2306,7 +2309,8 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
        if (flags & I915_VMA_LOCAL_BIND) {
                struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
 
-               if (appgtt->base.allocate_va_range) {
+               if (!(vma->flags & I915_VMA_LOCAL_BIND) &&
+                   appgtt->base.allocate_va_range) {
                        ret = appgtt->base.allocate_va_range(&appgtt->base,
                                                             vma->node.start,
                                                             vma->node.size);
index 11b12f4124920b07a65aaf7e02b81c8784bece46..5a7c63e64381e48a193610305973c468502565d2 100644 (file)
@@ -3051,10 +3051,14 @@ enum skl_disp_power_wells {
 #define CLKCFG_FSB_667                                 (3 << 0)        /* hrawclk 166 */
 #define CLKCFG_FSB_800                                 (2 << 0)        /* hrawclk 200 */
 #define CLKCFG_FSB_1067                                        (6 << 0)        /* hrawclk 266 */
+#define CLKCFG_FSB_1067_ALT                            (0 << 0)        /* hrawclk 266 */
 #define CLKCFG_FSB_1333                                        (7 << 0)        /* hrawclk 333 */
-/* Note, below two are guess */
-#define CLKCFG_FSB_1600                                        (4 << 0)        /* hrawclk 400 */
-#define CLKCFG_FSB_1600_ALT                            (0 << 0)        /* hrawclk 400 */
+/*
+ * Note that on at least on ELK the below value is reported for both
+ * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
+ * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
+ */
+#define CLKCFG_FSB_1333_ALT                            (4 << 0)        /* hrawclk 333 */
 #define CLKCFG_FSB_MASK                                        (7 << 0)
 #define CLKCFG_MEM_533                                 (1 << 4)
 #define CLKCFG_MEM_667                                 (2 << 4)
index dd3ad52b7dfeac5e7d6f8eb59ee18b372f20a77f..f29a226e24d8836d86c6e976ce07bcfc26a53c28 100644 (file)
@@ -1798,13 +1798,11 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
        case CLKCFG_FSB_800:
                return 200000;
        case CLKCFG_FSB_1067:
+       case CLKCFG_FSB_1067_ALT:
                return 266667;
        case CLKCFG_FSB_1333:
+       case CLKCFG_FSB_1333_ALT:
                return 333333;
-       /* these two are just a guess; one of them might be right */
-       case CLKCFG_FSB_1600:
-       case CLKCFG_FSB_1600_ALT:
-               return 400000;
        default:
                return 133333;
        }
index 3ffe8b1f1d486f5e7352f50a62091cbb60831c83..fc0ef492252ac7c93f7b7ccb4e6a4b95d30f6294 100644 (file)
@@ -410,11 +410,10 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
                val |= (ULPS_STATE_ENTER | DEVICE_READY);
                I915_WRITE(MIPI_DEVICE_READY(port), val);
 
-               /* Wait for ULPS Not active */
+               /* Wait for ULPS active */
                if (intel_wait_for_register(dev_priv,
-                               MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
-                               GLK_ULPS_NOT_ACTIVE, 20))
-                       DRM_ERROR("ULPS is still active\n");
+                               MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
+                       DRM_ERROR("ULPS not active\n");
 
                /* Exit ULPS */
                val = I915_READ(MIPI_DEVICE_READY(port));
index 25d8e76489e40ff989fd616386f03b36f9ba03fa..668f00480d97c0ff0418c19dfaaffec31fc65341 100644 (file)
@@ -63,6 +63,7 @@
 #include <linux/acpi.h>
 #include <linux/device.h>
 #include <linux/pci.h>
+#include <linux/pm_runtime.h>
 
 #include "i915_drv.h"
 #include <linux/delay.h>
@@ -121,6 +122,10 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
 
        kfree(rsc);
 
+       pm_runtime_forbid(&platdev->dev);
+       pm_runtime_set_active(&platdev->dev);
+       pm_runtime_enable(&platdev->dev);
+
        return platdev;
 
 err:
index 664b7fe206d65457cf3e7b1486a05b7e92493cb8..b11d3920b9a521b95142481106d420ac75643b26 100644 (file)
@@ -1809,10 +1809,6 @@ static int hdmi_lpe_audio_probe(struct platform_device *pdev)
        pdata->notify_pending = false;
        spin_unlock_irq(&pdata->lpe_audio_slock);
 
-       /* runtime PM isn't enabled as default, since it won't save much on
-        * BYT/CHT devices; user who want the runtime PM should adjust the
-        * power/ontrol and power/autosuspend_delay_ms sysfs entries instead
-        */
        pm_runtime_use_autosuspend(&pdev->dev);
        pm_runtime_mark_last_busy(&pdev->dev);
        pm_runtime_set_active(&pdev->dev);