drm/nouveau/fifo: separate object classes for dma channels

Future code will use the object class rather than chipset checks in order to
identify available channel features.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
index b0d3651fcabae021e958fe599027a42d7f2b89ae..848aa3bdacd15d1bebb95d490346b59226cd94d9 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
@@ -118,7 +118,10 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                return ret;
 
        switch (nv_mclass(parent)) {
+       case 0x006b:
        case 0x006e:
+       case 0x176e:
+       case 0x406e:
                ret = dmaeng->bind(dmaeng, *pobject, &dmaobj->base, &gpuobj);
                nouveau_object_ref(NULL, pobject);
                *pobject = nv_object(gpuobj);

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
index 7cd5d76dad29172a972712e4c8b728ffa7e2aaf8..ed771921e924a3b26da9a3bb083cb7652322b53c 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
@@ -247,7 +247,7 @@ nv04_fifo_ofuncs = {
 
 static struct nouveau_oclass
 nv04_fifo_sclass[] = {
-       { 0x006e, &nv04_fifo_ofuncs },
+       { 0x006b, &nv04_fifo_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
index f223eb9c773c78b8ddc3f43028981ea2d84fff56..347b91e134771f2d350e2ea236de6e080f787067 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
@@ -113,7 +113,7 @@ nv17_fifo_ofuncs = {
 
 static struct nouveau_oclass
 nv17_fifo_sclass[] = {
-       { 0x006e, &nv17_fifo_ofuncs },
+       { 0x176e, &nv17_fifo_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
index ce97c5ee4658c2cf0c7d266e304600a4389245ee..48114e6aa527d5439d50a9267db26d50b5ad1446 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
@@ -232,7 +232,7 @@ nv40_fifo_ofuncs = {
 
 static struct nouveau_oclass
 nv40_fifo_sclass[] = {
-       { 0x006e, &nv40_fifo_ofuncs },
+       { 0x406e, &nv40_fifo_ofuncs },
        {}
 };
 

diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index 9c6b0eba9699a87b8cfc8f33d6f5b3cd21d9daff..55b53ed8a0b8018c22551160f7d264df5c45cf2a 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -53,6 +53,7 @@ struct nv_dma_class {
 
 /* 006b: NV03_CHANNEL_DMA
  * 006e: NV10_CHANNEL_DMA
+ * 176e: NV17_CHANNEL_DMA
  * 406e: NV40_CHANNEL_DMA
  */
 

diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index 62c7edf08e5aaa33a66025ef13773d6b8a499959..cf61dc0226a3d9b0861c0f018315238342cfdf3b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -221,7 +221,7 @@ static int
 nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli,
                    u32 parent, u32 handle, struct nouveau_channel **pchan)
 {
-       static const u16 oclasses[] = { 0x006e, 0 };
+       static const u16 oclasses[] = { 0x406e, 0x176e, 0x006e, 0x006b, 0 };
        const u16 *oclass = oclasses;
        struct nv_channel_dma_class args;
        struct nouveau_channel *chan;
@@ -305,7 +305,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
        }
 
        /* initialise dma tracking parameters */
-       switch (nv_hclass(chan->object) & 0xffff) {
+       switch (nv_hclass(chan->object) & 0x00ff) {
+       case 0x006b:
        case 0x006e:
                chan->user_put = 0x40;
                chan->user_get = 0x44;