x86, intel: Output microcode revision in /proc/cpuinfo

I got a request to make it easier to determine the microcode
update level on Intel CPUs. This patch adds a new "microcode"
field to /proc/cpuinfo.

The microcode level is also outputed on fatal machine checks
together with the other CPUID model information.

I removed the respective code from the microcode update driver,
it just reads the field from cpu_data. Also when the microcode
is updated it fills in the new values too.

I had to add a memory barrier to native_cpuid to prevent it
being optimized away when the result is not used.

This turns out to clean up further code which already got this
information manually. This is done in followon patches.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 0d1171c9772937f4ec6980527aaebfdb9b6533cf..b650435ffb538d97df113a7b662975e88a60c375 100644 (file)
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -111,6 +111,7 @@ struct cpuinfo_x86 {
        /* Index into per_cpu list: */
        u16                     cpu_index;
 #endif
+       u32                     microcode;
 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 
 #define X86_VENDOR_INTEL       0
@@ -179,7 +180,8 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
              "=b" (*ebx),
              "=c" (*ecx),
              "=d" (*edx)
-           : "0" (*eax), "2" (*ecx));
+           : "0" (*eax), "2" (*ecx)
+           : "memory");
 }
 
 static inline void load_cr3(pgd_t *pgdir)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ed6086eedf1d2aaafd5a767d2cb56f5ed51aead9..26627a3a7148b3f53688a74a0842aba97dbfb9a2 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -47,6 +47,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 
+       if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
+               unsigned lower_word;
+
+               wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+               /* Required by the SDM */
+               sync_core();
+               rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
+       }
+
        /*
         * Atom erratum AAE44/AAF40/AAG38/AAH41:
         *

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 08363b0421222b92b5765bd2116cf9d4ecfca4d9..8af6fa47323311fc002d82f3f1c52133a54c283d 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -217,8 +217,13 @@ static void print_mce(struct mce *m)
                pr_cont("MISC %llx ", m->misc);
 
        pr_cont("\n");
-       pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
-               m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+       /*
+        * Note this output is parsed by external tools and old fields
+        * should not be changed.
+        */
+       pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %u\n",
+               m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
+               cpu_data(m->extcpu).microcode);
 
        /*
         * Print out human-readable details about the MCE error,

diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 62ac8cb6ba277218eec7cae7c7ef6d474d6406bc..6254fdae3e77b3f460f5f55540d398290f3e889e 100644 (file)
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -85,6 +85,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                seq_printf(m, "stepping\t: %d\n", c->x86_mask);
        else
                seq_printf(m, "stepping\t: unknown\n");
+       if (c->microcode)
+               seq_printf(m, "microcode\t: %u\n", c->microcode);
 
        if (cpu_has(c, X86_FEATURE_TSC)) {
                unsigned int freq = cpufreq_quick_get(cpu);

diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 1a1b606d3e92a879183cd720e3072b4b0832e579..3ca42d0e43a201f736a4ee3f0c5d5e9899933429 100644 (file)
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -161,12 +161,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
                csig->pf = 1 << ((val[1] >> 18) & 7);
        }
 
-       wrmsr(MSR_IA32_UCODE_REV, 0, 0);
-       /* see notes above for revision 1.07.  Apparent chip bug */
-       sync_core();
-       /* get the current revision from MSR 0x8B */
-       rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
-
+       csig->rev = c->microcode;
        pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
                cpu_num, csig->sig, csig->pf, csig->rev);
 
@@ -299,9 +294,9 @@ static int apply_microcode(int cpu)
        struct microcode_intel *mc_intel;
        struct ucode_cpu_info *uci;
        unsigned int val[2];
-       int cpu_num;
+       int cpu_num = raw_smp_processor_id();
+       struct cpuinfo_x86 *c = &cpu_data(cpu_num);
 
-       cpu_num = raw_smp_processor_id();
        uci = ucode_cpu_info + cpu;
        mc_intel = uci->mc;
 
@@ -317,7 +312,7 @@ static int apply_microcode(int cpu)
              (unsigned long) mc_intel->bits >> 16 >> 16);
        wrmsr(MSR_IA32_UCODE_REV, 0, 0);
 
-       /* see notes above for revision 1.07.  Apparent chip bug */
+       /* As documented in the SDM: Do a CPUID 1 here */
        sync_core();
 
        /* get the current revision from MSR 0x8B */
@@ -335,6 +330,7 @@ static int apply_microcode(int cpu)
                (mc_intel->hdr.date >> 16) & 0xff);
 
        uci->cpu_sig.rev = val[1];
+       c->microcode = val[1];
 
        return 0;
 }