uart: pl011: Rename regs with enumeration

Rename regs with enumeration to generalize register names.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index fd27e986b1dd3437dfd2560ec11efd8def7bf254..ee57e2bee9a1b709a223e57dc8f26d15f77eb2a7 100644 (file)
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -85,6 +85,25 @@ struct vendor_data {
        unsigned int (*get_fifosize)(struct amba_device *dev);
 };
 
+enum reg_idx {
+       REG_DR          = UART01x_DR,
+       REG_RSR         = UART01x_RSR,
+       REG_ST_DMAWM    = ST_UART011_DMAWM,
+       REG_FR          = UART01x_FR,
+       REG_ST_LCRH_RX  = ST_UART011_LCRH_RX,
+       REG_ILPR        = UART01x_ILPR,
+       REG_IBRD        = UART011_IBRD,
+       REG_FBRD        = UART011_FBRD,
+       REG_LCRH        = UART011_LCRH,
+       REG_CR          = UART011_CR,
+       REG_IFLS        = UART011_IFLS,
+       REG_IMSC        = UART011_IMSC,
+       REG_RIS         = UART011_RIS,
+       REG_MIS         = UART011_MIS,
+       REG_ICR         = UART011_ICR,
+       REG_DMACR       = UART011_DMACR,
+};
+
 static unsigned int get_fifosize_arm(struct amba_device *dev)
 {
        return amba_rev(dev) < 3 ? 16 : 32;
@@ -92,8 +111,8 @@ static unsigned int get_fifosize_arm(struct amba_device *dev)
 
 static struct vendor_data vendor_arm = {
        .ifls                   = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
-       .lcrh_tx                = UART011_LCRH,
-       .lcrh_rx                = UART011_LCRH,
+       .lcrh_tx                = REG_LCRH,
+       .lcrh_rx                = REG_LCRH,
        .oversampling           = false,
        .dma_threshold          = false,
        .cts_event_workaround   = false,
@@ -117,8 +136,8 @@ static unsigned int get_fifosize_st(struct amba_device *dev)
 
 static struct vendor_data vendor_st = {
        .ifls                   = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
-       .lcrh_tx                = ST_UART011_LCRH_TX,
-       .lcrh_rx                = ST_UART011_LCRH_RX,
+       .lcrh_tx                = REG_LCRH,
+       .lcrh_rx                = REG_ST_LCRH_RX,
        .oversampling           = true,
        .dma_threshold          = true,
        .cts_event_workaround   = true,
@@ -196,12 +215,12 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
        int fifotaken = 0;
 
        while (max_count--) {
-               status = readw(uap->port.membase + UART01x_FR);
+               status = readw(uap->port.membase + REG_FR);
                if (status & UART01x_FR_RXFE)
                        break;
 
                /* Take chars from the FIFO and update status */
-               ch = readw(uap->port.membase + UART01x_DR) |
+               ch = readw(uap->port.membase + REG_DR) |
                        UART_DUMMY_DR_RX;
                flag = TTY_NORMAL;
                uap->port.icount.rx++;
@@ -284,7 +303,7 @@ static void pl011_dma_probe(struct uart_amba_port *uap)
        struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
        struct device *dev = uap->port.dev;
        struct dma_slave_config tx_conf = {
-               .dst_addr = uap->port.mapbase + UART01x_DR,
+               .dst_addr = uap->port.mapbase + REG_DR,
                .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
                .direction = DMA_MEM_TO_DEV,
                .dst_maxburst = uap->fifosize >> 1,
@@ -339,7 +358,7 @@ static void pl011_dma_probe(struct uart_amba_port *uap)
 
        if (chan) {
                struct dma_slave_config rx_conf = {
-                       .src_addr = uap->port.mapbase + UART01x_DR,
+                       .src_addr = uap->port.mapbase + REG_DR,
                        .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
                        .direction = DMA_DEV_TO_MEM,
                        .src_maxburst = uap->fifosize >> 2,
@@ -438,7 +457,7 @@ static void pl011_dma_tx_callback(void *data)
 
        dmacr = uap->dmacr;
        uap->dmacr = dmacr & ~UART011_TXDMAE;
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
 
        /*
         * If TX DMA was disabled, it means that we've stopped the DMA for
@@ -552,7 +571,7 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap)
        dma_dev->device_issue_pending(chan);
 
        uap->dmacr |= UART011_TXDMAE;
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
        uap->dmatx.queued = true;
 
        /*
@@ -588,9 +607,9 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
         */
        if (uap->dmatx.queued) {
                uap->dmacr |= UART011_TXDMAE;
-               writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+               writew(uap->dmacr, uap->port.membase + REG_DMACR);
                uap->im &= ~UART011_TXIM;
-               writew(uap->im, uap->port.membase + UART011_IMSC);
+               writew(uap->im, uap->port.membase + REG_IMSC);
                return true;
        }
 
@@ -600,7 +619,7 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
         */
        if (pl011_dma_tx_refill(uap) > 0) {
                uap->im &= ~UART011_TXIM;
-               writew(uap->im, uap->port.membase + UART011_IMSC);
+               writew(uap->im, uap->port.membase + REG_IMSC);
                return true;
        }
        return false;
@@ -614,7 +633,7 @@ static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
 {
        if (uap->dmatx.queued) {
                uap->dmacr &= ~UART011_TXDMAE;
-               writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+               writew(uap->dmacr, uap->port.membase + REG_DMACR);
        }
 }
 
@@ -641,13 +660,13 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
                        if (pl011_dma_tx_refill(uap) > 0) {
                                uap->im &= ~UART011_TXIM;
                                writew(uap->im, uap->port.membase +
-                                      UART011_IMSC);
+                                      REG_IMSC);
                        } else
                                ret = false;
                } else if (!(uap->dmacr & UART011_TXDMAE)) {
                        uap->dmacr |= UART011_TXDMAE;
                        writew(uap->dmacr,
-                                      uap->port.membase + UART011_DMACR);
+                                      uap->port.membase + REG_DMACR);
                }
                return ret;
        }
@@ -658,9 +677,9 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
         */
        dmacr = uap->dmacr;
        uap->dmacr &= ~UART011_TXDMAE;
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
 
-       if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
+       if (readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF) {
                /*
                 * No space in the FIFO, so enable the transmit interrupt
                 * so we know when there is space.  Note that once we've
@@ -669,13 +688,13 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
                return false;
        }
 
-       writew(uap->port.x_char, uap->port.membase + UART01x_DR);
+       writew(uap->port.x_char, uap->port.membase + REG_DR);
        uap->port.icount.tx++;
        uap->port.x_char = 0;
 
        /* Success - restore the DMA state */
        uap->dmacr = dmacr;
-       writew(dmacr, uap->port.membase + UART011_DMACR);
+       writew(dmacr, uap->port.membase + REG_DMACR);
 
        return true;
 }
@@ -703,7 +722,7 @@ __acquires(&uap->port.lock)
                             DMA_TO_DEVICE);
                uap->dmatx.queued = false;
                uap->dmacr &= ~UART011_TXDMAE;
-               writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+               writew(uap->dmacr, uap->port.membase + REG_DMACR);
        }
 }
 
@@ -743,11 +762,11 @@ static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
        dma_async_issue_pending(rxchan);
 
        uap->dmacr |= UART011_RXDMAE;
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
        uap->dmarx.running = true;
 
        uap->im &= ~UART011_RXIM;
-       writew(uap->im, uap->port.membase + UART011_IMSC);
+       writew(uap->im, uap->port.membase + REG_IMSC);
 
        return 0;
 }
@@ -806,7 +825,7 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap,
        if (dma_count == pending && readfifo) {
                /* Clear any error flags */
                writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
-                      uap->port.membase + UART011_ICR);
+                      uap->port.membase + REG_ICR);
 
                /*
                 * If we read all the DMA'd characters, and we had an
@@ -854,7 +873,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
 
        /* Disable RX DMA - incoming data will wait in the FIFO */
        uap->dmacr &= ~UART011_RXDMAE;
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
        uap->dmarx.running = false;
 
        pending = sgbuf->sg.length - state.residue;
@@ -874,7 +893,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
                dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
                        "fall back to interrupt mode\n");
                uap->im |= UART011_RXIM;
-               writew(uap->im, uap->port.membase + UART011_IMSC);
+               writew(uap->im, uap->port.membase + REG_IMSC);
        }
 }
 
@@ -922,7 +941,7 @@ static void pl011_dma_rx_callback(void *data)
                dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
                        "fall back to interrupt mode\n");
                uap->im |= UART011_RXIM;
-               writew(uap->im, uap->port.membase + UART011_IMSC);
+               writew(uap->im, uap->port.membase + REG_IMSC);
        }
 }
 
@@ -935,7 +954,7 @@ static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
 {
        /* FIXME.  Just disable the DMA enable */
        uap->dmacr &= ~UART011_RXDMAE;
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
 }
 
 /*
@@ -979,7 +998,7 @@ static void pl011_dma_rx_poll(unsigned long args)
                spin_lock_irqsave(&uap->port.lock, flags);
                pl011_dma_rx_stop(uap);
                uap->im |= UART011_RXIM;
-               writew(uap->im, uap->port.membase + UART011_IMSC);
+               writew(uap->im, uap->port.membase + REG_IMSC);
                spin_unlock_irqrestore(&uap->port.lock, flags);
 
                uap->dmarx.running = false;
@@ -1041,7 +1060,7 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
 skip_rx:
        /* Turn on DMA error (RX/TX will be enabled on demand) */
        uap->dmacr |= UART011_DMAONERR;
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
 
        /*
         * ST Micro variants has some specific dma burst threshold
@@ -1050,7 +1069,8 @@ skip_rx:
         */
        if (uap->vendor->dma_threshold)
                writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
-                              uap->port.membase + ST_UART011_DMAWM);
+                               uap->port.membase + REG_ST_DMAWM);
+
 
        if (uap->using_rx_dma) {
                if (pl011_dma_rx_trigger_dma(uap))
@@ -1075,12 +1095,12 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
                return;
 
        /* Disable RX and TX DMA */
-       while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
+       while (readw(uap->port.membase + REG_FR) & UART01x_FR_BUSY)
                barrier();
 
        spin_lock_irq(&uap->port.lock);
        uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
-       writew(uap->dmacr, uap->port.membase + UART011_DMACR);
+       writew(uap->dmacr, uap->port.membase + REG_DMACR);
        spin_unlock_irq(&uap->port.lock);
 
        if (uap->using_tx_dma) {
@@ -1181,7 +1201,7 @@ static void pl011_stop_tx(struct uart_port *port)
            container_of(port, struct uart_amba_port, port);
 
        uap->im &= ~UART011_TXIM;
-       writew(uap->im, uap->port.membase + UART011_IMSC);
+       writew(uap->im, uap->port.membase + REG_IMSC);
        pl011_dma_tx_stop(uap);
 }
 
@@ -1191,7 +1211,7 @@ static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
 static void pl011_start_tx_pio(struct uart_amba_port *uap)
 {
        uap->im |= UART011_TXIM;
-       writew(uap->im, uap->port.membase + UART011_IMSC);
+       writew(uap->im, uap->port.membase + REG_IMSC);
        pl011_tx_chars(uap, false);
 }
 
@@ -1211,7 +1231,7 @@ static void pl011_stop_rx(struct uart_port *port)
 
        uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
                     UART011_PEIM|UART011_BEIM|UART011_OEIM);
-       writew(uap->im, uap->port.membase + UART011_IMSC);
+       writew(uap->im, uap->port.membase + REG_IMSC);
 
        pl011_dma_rx_stop(uap);
 }
@@ -1222,7 +1242,7 @@ static void pl011_enable_ms(struct uart_port *port)
            container_of(port, struct uart_amba_port, port);
 
        uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
-       writew(uap->im, uap->port.membase + UART011_IMSC);
+       writew(uap->im, uap->port.membase + REG_IMSC);
 }
 
 static void pl011_rx_chars(struct uart_amba_port *uap)
@@ -1242,7 +1262,7 @@ __acquires(&uap->port.lock)
                        dev_dbg(uap->port.dev, "could not trigger RX DMA job "
                                "fall back to interrupt mode again\n");
                        uap->im |= UART011_RXIM;
-                       writew(uap->im, uap->port.membase + UART011_IMSC);
+                       writew(uap->im, uap->port.membase + REG_IMSC);
                } else {
 #ifdef CONFIG_DMA_ENGINE
                        /* Start Rx DMA poll */
@@ -1263,10 +1283,10 @@ static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
                          bool from_irq)
 {
        if (unlikely(!from_irq) &&
-           readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
+           readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF)
                return false; /* unable to transmit character */
 
-       writew(c, uap->port.membase + UART01x_DR);
+       writew(c, uap->port.membase + REG_DR);
        uap->port.icount.tx++;
 
        return true;
@@ -1313,7 +1333,7 @@ static void pl011_modem_status(struct uart_amba_port *uap)
 {
        unsigned int status, delta;
 
-       status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+       status = readw(uap->port.membase + REG_FR) & UART01x_FR_MODEM_ANY;
 
        delta = status ^ uap->old_status;
        uap->old_status = status;
@@ -1341,15 +1361,15 @@ static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
                return;
 
        /* workaround to make sure that all bits are unlocked.. */
-       writew(0x00, uap->port.membase + UART011_ICR);
+       writew(0x00, uap->port.membase + REG_ICR);
 
        /*
         * WA: introduce 26ns(1 uart clk) delay before W1C;
         * single apb access will incur 2 pclk(133.12Mhz) delay,
         * so add 2 dummy reads
         */
-       dummy_read = readw(uap->port.membase + UART011_ICR);
-       dummy_read = readw(uap->port.membase + UART011_ICR);
+       dummy_read = readw(uap->port.membase + REG_ICR);
+       dummy_read = readw(uap->port.membase + REG_ICR);
 }
 
 static irqreturn_t pl011_int(int irq, void *dev_id)
@@ -1361,15 +1381,15 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
        int handled = 0;
 
        spin_lock_irqsave(&uap->port.lock, flags);
-       imsc = readw(uap->port.membase + UART011_IMSC);
-       status = readw(uap->port.membase + UART011_RIS) & imsc;
+       imsc = readw(uap->port.membase + REG_IMSC);
+       status = readw(uap->port.membase + REG_RIS) & imsc;
        if (status) {
                do {
                        check_apply_cts_event_workaround(uap);
 
                        writew(status & ~(UART011_TXIS|UART011_RTIS|
                                          UART011_RXIS),
-                              uap->port.membase + UART011_ICR);
+                              uap->port.membase + REG_ICR);
 
                        if (status & (UART011_RTIS|UART011_RXIS)) {
                                if (pl011_dma_rx_running(uap))
@@ -1386,7 +1406,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
                        if (pass_counter-- == 0)
                                break;
 
-                       status = readw(uap->port.membase + UART011_RIS) & imsc;
+                       status = readw(uap->port.membase + REG_RIS) & imsc;
                } while (status != 0);
                handled = 1;
        }
@@ -1400,7 +1420,7 @@ static unsigned int pl011_tx_empty(struct uart_port *port)
 {
        struct uart_amba_port *uap =
            container_of(port, struct uart_amba_port, port);
-       unsigned int status = readw(uap->port.membase + UART01x_FR);
+       unsigned int status = readw(uap->port.membase + REG_FR);
        return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
 }
 
@@ -1409,7 +1429,7 @@ static unsigned int pl011_get_mctrl(struct uart_port *port)
        struct uart_amba_port *uap =
            container_of(port, struct uart_amba_port, port);
        unsigned int result = 0;
-       unsigned int status = readw(uap->port.membase + UART01x_FR);
+       unsigned int status = readw(uap->port.membase + REG_FR);
 
 #define TIOCMBIT(uartbit, tiocmbit)    \
        if (status & uartbit)           \
@@ -1429,7 +1449,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
            container_of(port, struct uart_amba_port, port);
        unsigned int cr;
 
-       cr = readw(uap->port.membase + UART011_CR);
+       cr = readw(uap->port.membase + REG_CR);
 
 #define        TIOCMBIT(tiocmbit, uartbit)             \
        if (mctrl & tiocmbit)           \
@@ -1449,7 +1469,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
        }
 #undef TIOCMBIT
 
-       writew(cr, uap->port.membase + UART011_CR);
+       writew(cr, uap->port.membase + REG_CR);
 }
 
 static void pl011_break_ctl(struct uart_port *port, int break_state)
@@ -1477,7 +1497,7 @@ static void pl011_quiesce_irqs(struct uart_port *port)
            container_of(port, struct uart_amba_port, port);
        unsigned char __iomem *regs = uap->port.membase;
 
-       writew(readw(regs + UART011_MIS), regs + UART011_ICR);
+       writew(readw(regs + REG_MIS), regs + REG_ICR);
        /*
         * There is no way to clear TXIM as this is "ready to transmit IRQ", so
         * we simply mask it. start_tx() will unmask it.
@@ -1491,7 +1511,7 @@ static void pl011_quiesce_irqs(struct uart_port *port)
         * (including tx queue), so we're also fine with start_tx()'s caller
         * side.
         */
-       writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
+       writew(readw(regs + REG_IMSC) & ~UART011_TXIM, regs + REG_IMSC);
 }
 
 static int pl011_get_poll_char(struct uart_port *port)
@@ -1506,11 +1526,11 @@ static int pl011_get_poll_char(struct uart_port *port)
         */
        pl011_quiesce_irqs(port);
 
-       status = readw(uap->port.membase + UART01x_FR);
+       status = readw(uap->port.membase + REG_FR);
        if (status & UART01x_FR_RXFE)
                return NO_POLL_CHAR;
 
-       return readw(uap->port.membase + UART01x_DR);
+       return readw(uap->port.membase + REG_DR);
 }
 
 static void pl011_put_poll_char(struct uart_port *port,
@@ -1519,10 +1539,10 @@ static void pl011_put_poll_char(struct uart_port *port,
        struct uart_amba_port *uap =
            container_of(port, struct uart_amba_port, port);
 
-       while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
+       while (readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF)
                barrier();
 
-       writew(ch, uap->port.membase + UART01x_DR);
+       writew(ch, uap->port.membase + REG_DR);
 }
 
 #endif /* CONFIG_CONSOLE_POLL */
@@ -1547,14 +1567,14 @@ static int pl011_hwinit(struct uart_port *port)
 
        /* Clear pending error and receive interrupts */
        writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
-              UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
+              UART011_RTIS | UART011_RXIS, uap->port.membase + REG_ICR);
 
        /*
         * Save interrupts enable mask, and enable RX interrupts in case if
         * the interrupt is used for NMI entry.
         */
-       uap->im = readw(uap->port.membase + UART011_IMSC);
-       writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
+       uap->im = readw(uap->port.membase + REG_IMSC);
+       writew(UART011_RTIM | UART011_RXIM, uap->port.membase + REG_IMSC);
 
        if (dev_get_platdata(uap->port.dev)) {
                struct amba_pl011_data *plat;
@@ -1576,14 +1596,14 @@ static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
                 * to get this delay write read only register 10 times
                 */
                for (i = 0; i < 10; ++i)
-                       writew(0xff, uap->port.membase + UART011_MIS);
+                       writew(0xff, uap->port.membase + REG_MIS);
                writew(lcr_h, uap->port.membase + uap->lcrh_tx);
        }
 }
 
 static int pl011_allocate_irq(struct uart_amba_port *uap)
 {
-       writew(uap->im, uap->port.membase + UART011_IMSC);
+       writew(uap->im, uap->port.membase + REG_IMSC);
 
        return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
 }
@@ -1599,11 +1619,11 @@ static void pl011_enable_interrupts(struct uart_amba_port *uap)
 
        /* Clear out any spuriously appearing RX interrupts */
        writew(UART011_RTIS | UART011_RXIS,
-              uap->port.membase + UART011_ICR);
+              uap->port.membase + REG_ICR);
        uap->im = UART011_RTIM;
        if (!pl011_dma_rx_running(uap))
                uap->im |= UART011_RXIM;
-       writew(uap->im, uap->port.membase + UART011_IMSC);
+       writew(uap->im, uap->port.membase + REG_IMSC);
        spin_unlock_irq(&uap->port.lock);
 }
 
@@ -1622,21 +1642,22 @@ static int pl011_startup(struct uart_port *port)
        if (retval)
                goto clk_dis;
 
-       writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
+       writew(uap->vendor->ifls, uap->port.membase + REG_IFLS);
 
        spin_lock_irq(&uap->port.lock);
 
        /* restore RTS and DTR */
        cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
        cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
-       writew(cr, uap->port.membase + UART011_CR);
+       writew(cr, uap->port.membase + REG_CR);
 
        spin_unlock_irq(&uap->port.lock);
 
        /*
         * initialise the old status of the modem signals
         */
-       uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
+       uap->old_status = readw(uap->port.membase + REG_FR) &
+                       UART01x_FR_MODEM_ANY;
 
        /* Startup DMA */
        pl011_dma_startup(uap);
@@ -1693,11 +1714,11 @@ static void pl011_disable_uart(struct uart_amba_port *uap)
 
        uap->autorts = false;
        spin_lock_irq(&uap->port.lock);
-       cr = readw(uap->port.membase + UART011_CR);
+       cr = readw(uap->port.membase + REG_CR);
        uap->old_cr = cr;
        cr &= UART011_CR_RTS | UART011_CR_DTR;
        cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
-       writew(cr, uap->port.membase + UART011_CR);
+       writew(cr, uap->port.membase + REG_CR);
        spin_unlock_irq(&uap->port.lock);
 
        /*
@@ -1714,8 +1735,8 @@ static void pl011_disable_interrupts(struct uart_amba_port *uap)
 
        /* mask all interrupts and clear all pending ones */
        uap->im = 0;
-       writew(uap->im, uap->port.membase + UART011_IMSC);
-       writew(0xffff, uap->port.membase + UART011_ICR);
+       writew(uap->im, uap->port.membase + REG_IMSC);
+       writew(0xffff, uap->port.membase + REG_ICR);
 
        spin_unlock_irq(&uap->port.lock);
 }
@@ -1867,8 +1888,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
                pl011_enable_ms(port);
 
        /* first, disable everything */
-       old_cr = readw(port->membase + UART011_CR);
-       writew(0, port->membase + UART011_CR);
+       old_cr = readw(port->membase + REG_CR);
+       writew(0, port->membase + REG_CR);
 
        if (termios->c_cflag & CRTSCTS) {
                if (old_cr & UART011_CR_RTS)
@@ -1901,17 +1922,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
                        quot -= 2;
        }
        /* Set baud rate */
-       writew(quot & 0x3f, port->membase + UART011_FBRD);
-       writew(quot >> 6, port->membase + UART011_IBRD);
+       writew(quot & 0x3f, port->membase + REG_FBRD);
+       writew(quot >> 6, port->membase + REG_IBRD);
 
        /*
         * ----------v----------v----------v----------v-----
         * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
-        * UART011_FBRD & UART011_IBRD.
+        * REG_FBRD & REG_IBRD.
         * ----------^----------^----------^----------^-----
         */
        pl011_write_lcr_h(uap, lcr_h);
-       writew(old_cr, port->membase + UART011_CR);
+       writew(old_cr, port->membase + REG_CR);
 
        spin_unlock_irqrestore(&port->lock, flags);
 }
@@ -2052,9 +2073,9 @@ static void pl011_console_putchar(struct uart_port *port, int ch)
        struct uart_amba_port *uap =
            container_of(port, struct uart_amba_port, port);
 
-       while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
+       while (readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF)
                barrier();
-       writew(ch, uap->port.membase + UART01x_DR);
+       writew(ch, uap->port.membase + REG_DR);
 }
 
 static void
@@ -2079,10 +2100,10 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
         *      First save the CR then disable the interrupts
         */
        if (!uap->vendor->always_enabled) {
-               old_cr = readw(uap->port.membase + UART011_CR);
+               old_cr = readw(uap->port.membase + REG_CR);
                new_cr = old_cr & ~UART011_CR_CTSEN;
                new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
-               writew(new_cr, uap->port.membase + UART011_CR);
+               writew(new_cr, uap->port.membase + REG_CR);
        }
 
        uart_console_write(&uap->port, s, count, pl011_console_putchar);
@@ -2092,10 +2113,10 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
         *      and restore the TCR
         */
        do {
-               status = readw(uap->port.membase + UART01x_FR);
+               status = readw(uap->port.membase + REG_FR);
        } while (status & UART01x_FR_BUSY);
        if (!uap->vendor->always_enabled)
-               writew(old_cr, uap->port.membase + UART011_CR);
+               writew(old_cr, uap->port.membase + REG_CR);
 
        if (locked)
                spin_unlock(&uap->port.lock);
@@ -2108,7 +2129,7 @@ static void __init
 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
                             int *parity, int *bits)
 {
-       if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
+       if (readw(uap->port.membase + REG_CR) & UART01x_CR_UARTEN) {
                unsigned int lcr_h, ibrd, fbrd;
 
                lcr_h = readw(uap->port.membase + uap->lcrh_tx);
@@ -2126,13 +2147,13 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
                else
                        *bits = 8;
 
-               ibrd = readw(uap->port.membase + UART011_IBRD);
-               fbrd = readw(uap->port.membase + UART011_FBRD);
+               ibrd = readw(uap->port.membase + REG_IBRD);
+               fbrd = readw(uap->port.membase + REG_FBRD);
 
                *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
 
                if (uap->vendor->oversampling) {
-                       if (readw(uap->port.membase + UART011_CR)
+                       if (readw(uap->port.membase + REG_CR)
                                  & ST_UART011_CR_OVSFACT)
                                *baud *= 2;
                }
@@ -2204,10 +2225,10 @@ static struct console amba_console = {
 
 static void pl011_putc(struct uart_port *port, int c)
 {
-       while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
+       while (readl(port->membase + REG_FR) & UART01x_FR_TXFF)
                ;
-       writeb(c, port->membase + UART01x_DR);
-       while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
+       writeb(c, port->membase + REG_DR);
+       while (readl(port->membase + REG_FR) & UART01x_FR_BUSY)
                ;
 }
 
@@ -2334,8 +2355,8 @@ static int pl011_register_port(struct uart_amba_port *uap)
        int ret;
 
        /* Ensure interrupts from this UART are masked and cleared */
-       writew(0, uap->port.membase + UART011_IMSC);
-       writew(0xffff, uap->port.membase + UART011_ICR);
+       writew(0, uap->port.membase + REG_IMSC);
+       writew(0xffff, uap->port.membase + REG_ICR);
 
        if (!amba_reg.state) {
                ret = uart_register_driver(&amba_reg);