]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
ARM: kirkwood: Relocate PCIe device tree nodes
authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Fri, 26 Jul 2013 13:18:05 +0000 (10:18 -0300)
committerJason Cooper <jason@lakedaemon.net>
Tue, 6 Aug 2013 14:11:53 +0000 (14:11 +0000)
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of the ocp node, placing it directly
below the mbus. This is a more accurate representation of the hardware.

Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to
correspond to each MBus window.

In addition, we encode the PCIe memory and I/O apertures in the MBus
node, according to the MBus DT binding specification. The choice made
is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for
I/O space. These apertures can be changed in each per-board DT file.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
12 files changed:
arch/arm/boot/dts/kirkwood-6281.dtsi
arch/arm/boot/dts/kirkwood-6282.dtsi
arch/arm/boot/dts/kirkwood-db-88f6281.dts
arch/arm/boot/dts/kirkwood-db-88f6282.dts
arch/arm/boot/dts/kirkwood-db.dtsi
arch/arm/boot/dts/kirkwood-iconnect.dts
arch/arm/boot/dts/kirkwood-mplcec4.dts
arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
arch/arm/boot/dts/kirkwood-nsa310.dts
arch/arm/boot/dts/kirkwood-ts219-6282.dts
arch/arm/boot/dts/kirkwood-ts219.dtsi
arch/arm/boot/dts/kirkwood.dtsi

index 1e5bef0bead7e39d95a31b8fade75c112081c9a3..650ef30e1856f9591f32a445f279489c82b22b68 100644 (file)
@@ -1,4 +1,39 @@
 / {
+       mbus {
+               pcie-controller {
+                       compatible = "marvell,kirkwood-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges =
+                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 9>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 2>;
+                               status = "disabled";
+                       };
+               };
+       };
+
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
                        compatible = "marvell,88f6281-pinctrl";
                        };
                };
 
-               pcie-controller {
-                       compatible = "marvell,kirkwood-pcie";
-                       status = "disabled";
-                       device_type = "pci";
-
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-
-                       bus-range = <0x00 0xff>;
-
-                       ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
-                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                       pcie@1,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-                               reg = <0x0800 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               #interrupt-cells = <1>;
-                               ranges;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &intc 9>;
-                               marvell,pcie-port = <0>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gate_clk 2>;
-                               status = "disabled";
-                       };
-               };
-
                rtc@10300 {
                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                        reg = <0x10300 0x20>;
index a63a1113726274f8ff56060c7a6abe41dd01b2d9..3933a331ddc2ed8d8f71b58c4cc7389e7e860220 100644 (file)
@@ -1,4 +1,59 @@
 / {
+       mbus {
+               pcie-controller {
+                       compatible = "marvell,kirkwood-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges =
+                              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
+                               0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
+                               0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 9>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 2>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 10>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 18>;
+                               status = "disabled";
+                       };
+               };
+       };
        ocp@f1000000 {
 
                pinctrl: pinctrl@10000 {
                        status = "disabled";
                };
 
-               pcie-controller {
-                       compatible = "marvell,kirkwood-pcie";
-                       status = "disabled";
-                       device_type = "pci";
-
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-
-                       bus-range = <0x00 0xff>;
-
-                       ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
-                                 0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
-                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                       pcie@1,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-                               reg = <0x0800 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               #interrupt-cells = <1>;
-                               ranges;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &intc 9>;
-                               marvell,pcie-port = <0>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gate_clk 2>;
-                               status = "disabled";
-                       };
-
-                       pcie@2,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
-                               reg = <0x1000 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               #interrupt-cells = <1>;
-                               ranges;
-                               interrupt-map-mask = <0 0 0 0>;
-                               interrupt-map = <0 0 0 0 &intc 10>;
-                               marvell,pcie-port = <1>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gate_clk 18>;
-                               status = "disabled";
-                       };
-               };
        };
 };
index f420cbe856f787a3cb82bf1adc121191f062b312..72c4b0a0366ffcd656f16456c430b067ff814b5a 100644 (file)
@@ -18,7 +18,8 @@
        model = "Marvell DB-88F6281-BP Development Board";
        compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
-       ocp@f1000000 {
+       mbus {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
                pcie-controller {
                        status = "okay";
 
index c5df86607412911f99265a536316535decc09610..36c411d349268e41e05d220f3d56e2d82553506e 100644 (file)
@@ -18,7 +18,8 @@
        model = "Marvell DB-88F6282-BP Development Board";
        compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
 
-       ocp@f1000000 {
+       mbus {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
                pcie-controller {
                        status = "okay";
 
index 29bd98efc824699e9a87b88f815f1f538671e3fe..45c1bf74ac00ce958968bf14077c58c886420565 100644 (file)
                        cd-gpios = <&gpio1 6 0>;
                        status = "okay";
                };
-
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@1,0 {
-                               status = "okay";
-                       };
-               };
        };
 };
index 1a984876b428cd58bb3d0aab92c9b97d720c9147..8314118b6b8a33d96c75c76e563ae92f61481646 100644 (file)
                linux,initrd-end   = <0x4800000>;
        };
 
+       mbus {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+               pcie-controller {
+                       status = "okay";
+
+                       pcie@1,0 {
+                               status = "okay";
+                       };
+               };
+       };
+
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
                        pmx_button_reset: pmx-button-reset {
                                reg = <0x980000 0x1f400000>;
                        };
                };
-
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@1,0 {
-                               status = "okay";
-                       };
-               };
        };
 
        gpio-leds {
index 382ad99ab2c6fb0b09d4fdd28d8cbeacff76c8d1..21f1954c9e54f690c5ac8202e309130ae9ffa3a6 100644 (file)
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
         };
 
+       mbus {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+               pcie-controller {
+                       status = "okay";
+
+                       pcie@1,0 {
+                               status = "okay";
+                       };
+               };
+       };
+
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
                        pmx_led_health: pmx-led-health {
                        cd-gpios = <&gpio1 15 1>;
                        /* No WP GPIO */
                };
-
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@1,0 {
-                               status = "okay";
-                       };
-               };
        };
 
        gpio-leds {
index 8be68bda818208b8e37b226753b4766b5601257f..84ff31cfbcdc6909443d096572cd62148a2908c3 100644 (file)
                bootargs = "console=ttyS0,115200n8 earlyprintk";
        };
 
+       mbus {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+               pcie-controller {
+                       status = "okay";
+
+                       pcie@1,0 {
+                               status = "okay";
+                       };
+               };
+       };
+
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
                        pmx_button_power: pmx-button-power {
                        status = "okay";
                        nr-ports = <2>;
                };
-
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@1,0 {
-                               status = "okay";
-                       };
-               };
        };
 
        gpio-leds {
index 8fd683c34142f1282f2f2ad72cf06a4d07180948..bd7f05f6aa9631bb802e28d1fcc7a7b71d3bac63 100644 (file)
                bootargs = "console=ttyS0,115200";
        };
 
+       mbus {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+               pcie-controller {
+                       status = "okay";
+
+                       pcie@1,0 {
+                               status = "okay";
+                       };
+               };
+       };
+
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
                        pinctrl-0 = <&pmx_unknown>;
                                reg = <0x5040000 0x2fc0000>;
                        };
                };
-
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@1,0 {
-                               status = "okay";
-                       };
-               };
        };
 
        gpio_keys {
index 7d6cc867678ebe6473600564fc675b8534214538..04f6fe106bb57b4410193374c1df9c0d0fa9536b 100644 (file)
@@ -5,6 +5,17 @@
 #include "kirkwood-ts219.dtsi"
 
 / {
+       mbus {
+               ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+               pcie-controller {
+                       status = "okay";
+
+                       pcie@2,0 {
+                               status = "okay";
+                       };
+               };
+       };
+
        ocp@f1000000 {
                pinctrl: pinctrl@10000 {
 
                                marvell,function = "gpio";
                        };
                };
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@2,0 {
-                               status = "okay";
-                       };
-               };
-
        };
 
        gpio_keys {
index 0c9a94cd666c597dab629b8a9a7908f02e82abd6..7019cf675df26dec61632c979a05ed51d9f04ef4 100644 (file)
                bootargs = "console=ttyS0,115200n8";
        };
 
+       mbus {
+               pcie-controller {
+                       status = "okay";
+
+                       pcie@1,0 {
+                               status = "okay";
+                       };
+               };
+       };
+
        ocp@f1000000 {
                i2c@11000 {
                        status = "okay";
                        status = "okay";
                        nr-ports = <2>;
                };
-               pcie-controller {
-                       status = "okay";
-
-                       pcie@1,0 {
-                               status = "okay";
-                       };
-               };
        };
 };
index 5003c8302b769edf8d66b6c5f43818b895d0e1cd..70f414d9bd9ac8e99a1dd14e28f564f96f3d2634 100644 (file)
 
        mbus {
                compatible = "marvell,kirkwood-mbus", "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <1>;
                controller = <&mbusc>;
+               pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
+               pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */
        };
 
        ocp@f1000000 {
                compatible = "simple-bus";
                ranges = <0x00000000 0xf1000000 0x0100000
-                         0xe0000000 0xe0000000 0x8100000 /* PCIE */
                          0xf4000000 0xf4000000 0x0000400
                          0xf5000000 0xf5000000 0x0000400>;
                #address-cells = <1>;