sh: clkfwk: Add MSTP bits to SH7785 clock framework.

This plugs in all of the MSTP functions in to the clock framework,
and hands them off to the platform devices that want them.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index c499d470b8c9268de645bc05acfdb5bfecca48ad..64c93cb3d685ac9a4c12d5647829c374fec4711e 100644 (file)
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -36,6 +36,9 @@ struct clk {
        unsigned long           rate;
        unsigned long           flags;
 
+       void __iomem            *enable_reg;
+       unsigned int            enable_bit;
+
        unsigned long           arch_flags;
        void                    *priv;
        struct dentry           *dentry;

diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 686477f8ae5bb08e17237cc71a2e5dec05f14fc1..012d23476a72cd01cb4c64d35404a104ca177a57 100644 (file)
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -39,7 +39,7 @@ static DEFINE_MUTEX(clock_list_sem);
 /* Used for clocks that always have same value as the parent clock */
 unsigned long followparent_recalc(struct clk *clk)
 {
-       return clk->parent->rate;
+       return clk->parent ? clk->parent->rate : 0;
 }
 
 int clk_reparent(struct clk *child, struct clk *parent)
@@ -512,7 +512,7 @@ static int clk_debugfs_register_one(struct clk *c)
        char *p = s;
 
        p += sprintf(p, "%s", c->name);
-       if (c->id > 0)
+       if (c->id >= 0)
                sprintf(p, ":%d", c->id);
        d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
        if (!d)

diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index b7a32dd1b2dbe29b994385cb4235c8d06a7e7b12..cf042b53b3aeb89413356fb8c873d33d3d8d4ced 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -228,12 +228,75 @@ static struct clk *clks[] = {
        &umem_clk,
 };
 
+static int mstpcr_clk_enable(struct clk *clk)
+{
+       __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
+                    clk->enable_reg);
+       return 0;
+}
+
+static void mstpcr_clk_disable(struct clk *clk)
+{
+       __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
+                    clk->enable_reg);
+}
+
+static struct clk_ops mstpcr_clk_ops = {
+       .enable         = mstpcr_clk_enable,
+       .disable        = mstpcr_clk_disable,
+       .recalc         = followparent_recalc,
+};
+
+#define MSTPCR0                0xffc80030
+#define MSTPCR1                0xffc80034
+
+#define CLK(_name, _id, _parent, _enable_reg,          \
+           _enable_bit, _flags)                        \
+{                                                      \
+       .name           = _name,                        \
+       .id             = _id,                          \
+       .parent         = _parent,                      \
+       .enable_reg     = (void __iomem *)_enable_reg,  \
+       .enable_bit     = _enable_bit,                  \
+       .flags          = _flags,                       \
+       .ops            = &mstpcr_clk_ops,              \
+}
+
+static struct clk mstpcr_clks[] = {
+       /* MSTPCR0 */
+       CLK("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0),
+       CLK("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0),
+       CLK("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0),
+       CLK("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0),
+       CLK("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0),
+       CLK("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0),
+       CLK("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0),
+       CLK("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0),
+       CLK("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0),
+       CLK("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0),
+       CLK("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0),
+       CLK("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0),
+       CLK("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0),
+       CLK("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0),
+       CLK("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0),
+       CLK("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0),
+
+       /* MSTPCR1 */
+       CLK("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
+       CLK("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
+       CLK("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
+       CLK("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
+       CLK("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
+};
+
 int __init arch_clk_init(void)
 {
        int i, ret = 0;
 
        for (i = 0; i < ARRAY_SIZE(clks); i++)
                ret |= clk_register(clks[i]);
+       for (i = 0; i < ARRAY_SIZE(mstpcr_clks); i++)
+               ret |= clk_register(&mstpcr_clks[i]);
 
        return ret;
 }

diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index d7e77bc77e288aa7ed5385c5df3ae824c706ea28..af561402570bdb411a026a1127b5e42a54fdc524 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,7 +20,7 @@ static struct sh_timer_config tmu0_platform_data = {
        .name = "TMU0",
        .channel_offset = 0x04,
        .timer_bit = 0,
-       .clk = "peripheral_clk",
+       .clk = "tmu012_fck",
        .clockevent_rating = 200,
 };
 
@@ -51,7 +51,7 @@ static struct sh_timer_config tmu1_platform_data = {
        .name = "TMU1",
        .channel_offset = 0x10,
        .timer_bit = 1,
-       .clk = "peripheral_clk",
+       .clk = "tmu012_fck",
        .clocksource_rating = 200,
 };
 
@@ -82,7 +82,7 @@ static struct sh_timer_config tmu2_platform_data = {
        .name = "TMU2",
        .channel_offset = 0x1c,
        .timer_bit = 2,
-       .clk = "peripheral_clk",
+       .clk = "tmu012_fck",
 };
 
 static struct resource tmu2_resources[] = {
@@ -112,7 +112,7 @@ static struct sh_timer_config tmu3_platform_data = {
        .name = "TMU3",
        .channel_offset = 0x04,
        .timer_bit = 0,
-       .clk = "peripheral_clk",
+       .clk = "tmu345_fck",
 };
 
 static struct resource tmu3_resources[] = {
@@ -142,7 +142,7 @@ static struct sh_timer_config tmu4_platform_data = {
        .name = "TMU4",
        .channel_offset = 0x10,
        .timer_bit = 1,
-       .clk = "peripheral_clk",
+       .clk = "tmu345_fck",
 };
 
 static struct resource tmu4_resources[] = {
@@ -172,7 +172,7 @@ static struct sh_timer_config tmu5_platform_data = {
        .name = "TMU5",
        .channel_offset = 0x1c,
        .timer_bit = 2,
-       .clk = "peripheral_clk",
+       .clk = "tmu345_fck",
 };
 
 static struct resource tmu5_resources[] = {
@@ -204,31 +204,37 @@ static struct plat_sci_port sci_platform_data[] = {
                .flags          = UPF_BOOT_AUTOCONF,
                .type           = PORT_SCIF,
                .irqs           = { 40, 40, 40, 40 },
+               .clk            = "scif_fck",
        }, {
                .mapbase        = 0xffeb0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .type           = PORT_SCIF,
                .irqs           = { 44, 44, 44, 44 },
+               .clk            = "scif_fck",
        }, {
                .mapbase        = 0xffec0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .type           = PORT_SCIF,
                .irqs           = { 60, 60, 60, 60 },
+               .clk            = "scif_fck",
        }, {
                .mapbase        = 0xffed0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .type           = PORT_SCIF,
                .irqs           = { 61, 61, 61, 61 },
+               .clk            = "scif_fck",
        }, {
                .mapbase        = 0xffee0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .type           = PORT_SCIF,
                .irqs           = { 62, 62, 62, 62 },
+               .clk            = "scif_fck",
        }, {
                .mapbase        = 0xffef0000,
                .flags          = UPF_BOOT_AUTOCONF,
                .type           = PORT_SCIF,
                .irqs           = { 63, 63, 63, 63 },
+               .clk            = "scif_fck",
        }, {
                .flags = 0,
        }