ARM: dts: imx6q-arm2: add pinctrl state for usdhc

Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 3fabe921f7b482122e1e2e5b7ded4342f7dd1f54..97893f5cab92908da14106762c16ec76d247f253 100644 (file)
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -32,12 +32,16 @@
                                cd-gpios = <&gpio6 11 0>;
                                wp-gpios = <&gpio6 14 0>;
                                vmmc-supply = <&reg_3p3v>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usdhc3_1>;
                                status = "okay";
                        };
 
                        usdhc@0219c000 { /* uSDHC4 */
                                fsl,card-wired;
                                vmmc-supply = <&reg_3p3v>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usdhc4_1>;
                                status = "okay";
                        };
 

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 56c5304e4cbcc1f6e636fa02bf1a4de1e569ab64..72ccd1d21cd9292a73ab28754705c37c21bc5294 100644 (file)
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -470,7 +470,39 @@
                        };
 
                        iomuxc@020e0000 {
+                               compatible = "fsl,imx6q-iomuxc";
                                reg = <0x020e0000 0x4000>;
+
+                               /* shared pinctrl settings */
+                               usdhc3 {
+                                       pinctrl_usdhc3_1: usdhc3grp-1 {
+                                               fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+                                                           1281 0x10059        /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+                                                           1289 0x17059        /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+                                                           1297 0x17059        /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+                                                           1305 0x17059        /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+                                                           1312 0x17059        /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                           1265 0x17059        /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+                                                           1257 0x17059        /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+                                                           1249 0x17059        /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+                                                           1241 0x17059>;      /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                       };
+                               };
+
+                               usdhc4 {
+                                       pinctrl_usdhc4_1: usdhc4grp-1 {
+                                               fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                                           1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                                           1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                                           1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                                           1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                                           1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                           1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+                                                           1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+                                                           1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+                                                           1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                       };
+                               };
                        };
 
                        dcic@020e4000 { /* DCIC1 */