config MFD_ASIC3
bool "Support for Compaq ASIC3"
depends on GENERIC_HARDIRQS && GPIOLIB && ARM
+ select MFD_CORE
---help---
This driver supports the ASIC3 multifunction chip found on many
PDAs (mainly iPAQ and HTC based ones)
depends on I2C
help
Support for the Wolfson Microelecronics WM8400 PMIC and audio
- CODEC. This driver adds provides common support for accessing
+ CODEC. This driver provides common support for accessing
the device, additional drivers must be enabled in order to use
the functionality of the device.
Say yes here if you want to include support GPIO for pins on
the PCF50633 chip.
+config AB3100_CORE
+ tristate "ST-Ericsson AB3100 Mixed Signal Circuit core functions"
+ depends on I2C
+ default y if ARCH_U300
+ help
+ Select this to enable the AB3100 Mixed Signal IC core
+ functionality. This connects to a AB3100 on the I2C bus
+ and expose a number of symbols needed for dependent devices
+ to read and write registers and subscribe to events from
+ this multi-functional IC. This is needed to use other features
+ of the AB3100 such as battery-backed RTC, charging control,
+ LEDs, vibrator, system power and temperature, power management
+ and ALSA sound.
+
+config EZX_PCAP
+ bool "PCAP Support"
+ depends on GENERIC_HARDIRQS && SPI_MASTER
+ help
+ This enables the PCAP ASIC present on EZX Phones. This is
+ needed for MMC, TouchScreen, Sound, USB, etc..
+
endmenu
menu "Multimedia Capabilities Port drivers"
obj-$(CONFIG_MFD_CORE) += mfd-core.o
+obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o
+
obj-$(CONFIG_MCP) += mcp-core.o
obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o
obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
-obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
\ No newline at end of file
+obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
+obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
--- /dev/null
+/*
+ * Copyright (C) 2007-2009 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Low-level core for exclusive access to the AB3100 IC on the I2C bus
+ * and some basic chip-configuration.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/list.h>
+#include <linux/notifier.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/mfd/ab3100.h>
+
+/* These are the only registers inside AB3100 used in this main file */
+
+/* Interrupt event registers */
+#define AB3100_EVENTA1 0x21
+#define AB3100_EVENTA2 0x22
+#define AB3100_EVENTA3 0x23
+
+/* AB3100 DAC converter registers */
+#define AB3100_DIS 0x00
+#define AB3100_D0C 0x01
+#define AB3100_D1C 0x02
+#define AB3100_D2C 0x03
+#define AB3100_D3C 0x04
+
+/* Chip ID register */
+#define AB3100_CID 0x20
+
+/* AB3100 interrupt registers */
+#define AB3100_IMRA1 0x24
+#define AB3100_IMRA2 0x25
+#define AB3100_IMRA3 0x26
+#define AB3100_IMRB1 0x2B
+#define AB3100_IMRB2 0x2C
+#define AB3100_IMRB3 0x2D
+
+/* System Power Monitoring and control registers */
+#define AB3100_MCA 0x2E
+#define AB3100_MCB 0x2F
+
+/* SIM power up */
+#define AB3100_SUP 0x50
+
+/*
+ * I2C communication
+ *
+ * The AB3100 is usually assigned address 0x48 (7-bit)
+ * The chip is defined in the platform i2c_board_data section.
+ */
+static unsigned short normal_i2c[] = { 0x48, I2C_CLIENT_END };
+I2C_CLIENT_INSMOD_1(ab3100);
+
+u8 ab3100_get_chip_type(struct ab3100 *ab3100)
+{
+ u8 chip = ABUNKNOWN;
+
+ switch (ab3100->chip_id & 0xf0) {
+ case 0xa0:
+ chip = AB3000;
+ break;
+ case 0xc0:
+ chip = AB3100;
+ break;
+ }
+ return chip;
+}
+EXPORT_SYMBOL(ab3100_get_chip_type);
+
+int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval)
+{
+ u8 regandval[2] = {reg, regval};
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /*
+ * A two-byte write message with the first byte containing the register
+ * number and the second byte containing the value to be written
+ * effectively sets a register in the AB3100.
+ */
+ err = i2c_master_send(ab3100->i2c_client, regandval, 2);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (write register): %d\n",
+ err);
+ } else if (err != 2) {
+ dev_err(ab3100->dev,
+ "write error (write register) "
+ "%d bytes transferred (expected 2)\n",
+ err);
+ err = -EIO;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+ mutex_unlock(&ab3100->access_mutex);
+ return 0;
+}
+EXPORT_SYMBOL(ab3100_set_register);
+
+/*
+ * The test registers exist at an I2C bus address up one
+ * from the ordinary base. They are not supposed to be used
+ * in production code, but sometimes you have to do that
+ * anyway. It's currently only used from this file so declare
+ * it static and do not export.
+ */
+static int ab3100_set_test_register(struct ab3100 *ab3100,
+ u8 reg, u8 regval)
+{
+ u8 regandval[2] = {reg, regval};
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ err = i2c_master_send(ab3100->testreg_client, regandval, 2);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (write test register): %d\n",
+ err);
+ } else if (err != 2) {
+ dev_err(ab3100->dev,
+ "write error (write test register) "
+ "%d bytes transferred (expected 2)\n",
+ err);
+ err = -EIO;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+ mutex_unlock(&ab3100->access_mutex);
+
+ return err;
+}
+
+int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval)
+{
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /*
+ * AB3100 require an I2C "stop" command between each message, else
+ * it will not work. The only way of achieveing this with the
+ * message transport layer is to send the read and write messages
+ * separately.
+ */
+ err = i2c_master_send(ab3100->i2c_client, ®, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (send register address): %d\n",
+ err);
+ goto get_reg_out_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (send register address) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_reg_out_unlock;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+
+ err = i2c_master_recv(ab3100->i2c_client, regval, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (read register): %d\n",
+ err);
+ goto get_reg_out_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (read register) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_reg_out_unlock;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+
+ get_reg_out_unlock:
+ mutex_unlock(&ab3100->access_mutex);
+ return err;
+}
+EXPORT_SYMBOL(ab3100_get_register);
+
+int ab3100_get_register_page(struct ab3100 *ab3100,
+ u8 first_reg, u8 *regvals, u8 numregs)
+{
+ int err;
+
+ if (ab3100->chip_id == 0xa0 ||
+ ab3100->chip_id == 0xa1)
+ /* These don't support paged reads */
+ return -EIO;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /*
+ * Paged read also require an I2C "stop" command.
+ */
+ err = i2c_master_send(ab3100->i2c_client, &first_reg, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (send first register address): %d\n",
+ err);
+ goto get_reg_page_out_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (send first register address) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_reg_page_out_unlock;
+ }
+
+ err = i2c_master_recv(ab3100->i2c_client, regvals, numregs);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (read register page): %d\n",
+ err);
+ goto get_reg_page_out_unlock;
+ } else if (err != numregs) {
+ dev_err(ab3100->dev,
+ "write error (read register page) "
+ "%d bytes transferred (expected %d)\n",
+ err, numregs);
+ err = -EIO;
+ goto get_reg_page_out_unlock;
+ }
+
+ /* All is well */
+ err = 0;
+
+ get_reg_page_out_unlock:
+ mutex_unlock(&ab3100->access_mutex);
+ return err;
+}
+EXPORT_SYMBOL(ab3100_get_register_page);
+
+int ab3100_mask_and_set_register(struct ab3100 *ab3100,
+ u8 reg, u8 andmask, u8 ormask)
+{
+ u8 regandval[2] = {reg, 0};
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /* First read out the target register */
+ err = i2c_master_send(ab3100->i2c_client, ®, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (maskset send address): %d\n",
+ err);
+ goto get_maskset_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (maskset send address) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_maskset_unlock;
+ }
+
+ err = i2c_master_recv(ab3100->i2c_client, ®andval[1], 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (maskset read register): %d\n",
+ err);
+ goto get_maskset_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (maskset read register) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_maskset_unlock;
+ }
+
+ /* Modify the register */
+ regandval[1] &= andmask;
+ regandval[1] |= ormask;
+
+ /* Write the register */
+ err = i2c_master_send(ab3100->i2c_client, regandval, 2);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (write register): %d\n",
+ err);
+ goto get_maskset_unlock;
+ } else if (err != 2) {
+ dev_err(ab3100->dev,
+ "write error (write register) "
+ "%d bytes transferred (expected 2)\n",
+ err);
+ err = -EIO;
+ goto get_maskset_unlock;
+ }
+
+ /* All is well */
+ err = 0;
+
+ get_maskset_unlock:
+ mutex_unlock(&ab3100->access_mutex);
+ return err;
+}
+EXPORT_SYMBOL(ab3100_mask_and_set_register);
+
+/*
+ * Register a simple callback for handling any AB3100 events.
+ */
+int ab3100_event_register(struct ab3100 *ab3100,
+ struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&ab3100->event_subscribers,
+ nb);
+}
+EXPORT_SYMBOL(ab3100_event_register);
+
+/*
+ * Remove a previously registered callback.
+ */
+int ab3100_event_unregister(struct ab3100 *ab3100,
+ struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(&ab3100->event_subscribers,
+ nb);
+}
+EXPORT_SYMBOL(ab3100_event_unregister);
+
+
+int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
+ u32 *fatevent)
+{
+ if (!ab3100->startup_events_read)
+ return -EAGAIN; /* Try again later */
+ *fatevent = ab3100->startup_events;
+ return 0;
+}
+EXPORT_SYMBOL(ab3100_event_registers_startup_state_get);
+
+/* Interrupt handling worker */
+static void ab3100_work(struct work_struct *work)
+{
+ struct ab3100 *ab3100 = container_of(work, struct ab3100, work);
+ u8 event_regs[3];
+ u32 fatevent;
+ int err;
+
+ err = ab3100_get_register_page(ab3100, AB3100_EVENTA1,
+ event_regs, 3);
+ if (err)
+ goto err_event_wq;
+
+ fatevent = (event_regs[0] << 16) |
+ (event_regs[1] << 8) |
+ event_regs[2];
+
+ if (!ab3100->startup_events_read) {
+ ab3100->startup_events = fatevent;
+ ab3100->startup_events_read = true;
+ }
+ /*
+ * The notified parties will have to mask out the events
+ * they're interested in and react to them. They will be
+ * notified on all events, then they use the fatevent value
+ * to determine if they're interested.
+ */
+ blocking_notifier_call_chain(&ab3100->event_subscribers,
+ fatevent, NULL);
+
+ dev_dbg(ab3100->dev,
+ "IRQ Event: 0x%08x\n", fatevent);
+
+ /* By now the IRQ should be acked and deasserted so enable it again */
+ enable_irq(ab3100->i2c_client->irq);
+ return;
+
+ err_event_wq:
+ dev_dbg(ab3100->dev,
+ "error in event workqueue\n");
+ /* Enable the IRQ anyway, what choice do we have? */
+ enable_irq(ab3100->i2c_client->irq);
+ return;
+}
+
+static irqreturn_t ab3100_irq_handler(int irq, void *data)
+{
+ struct ab3100 *ab3100 = data;
+ /*
+ * Disable the IRQ and dispatch a worker to handle the
+ * event. Since the chip resides on I2C this is slow
+ * stuff and we will re-enable the interrupts once th
+ * worker has finished.
+ */
+ disable_irq(ab3100->i2c_client->irq);
+ schedule_work(&ab3100->work);
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_DEBUG_FS
+/*
+ * Some debugfs entries only exposed if we're using debug
+ */
+static int ab3100_registers_print(struct seq_file *s, void *p)
+{
+ struct ab3100 *ab3100 = s->private;
+ u8 value;
+ u8 reg;
+
+ seq_printf(s, "AB3100 registers:\n");
+
+ for (reg = 0; reg < 0xff; reg++) {
+ ab3100_get_register(ab3100, reg, &value);
+ seq_printf(s, "[0x%x]: 0x%x\n", reg, value);
+ }
+ return 0;
+}
+
+static int ab3100_registers_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, ab3100_registers_print, inode->i_private);
+}
+
+static const struct file_operations ab3100_registers_fops = {
+ .open = ab3100_registers_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .owner = THIS_MODULE,
+};
+
+struct ab3100_get_set_reg_priv {
+ struct ab3100 *ab3100;
+ bool mode;
+};
+
+static int ab3100_get_set_reg_open_file(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static int ab3100_get_set_reg(struct file *file,
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct ab3100_get_set_reg_priv *priv = file->private_data;
+ struct ab3100 *ab3100 = priv->ab3100;
+ char buf[32];
+ int buf_size;
+ int regp;
+ unsigned long user_reg;
+ int err;
+ int i = 0;
+
+ /* Get userspace string and assure termination */
+ buf_size = min(count, (sizeof(buf)-1));
+ if (copy_from_user(buf, user_buf, buf_size))
+ return -EFAULT;
+ buf[buf_size] = 0;
+
+ /*
+ * The idea is here to parse a string which is either
+ * "0xnn" for reading a register, or "0xaa 0xbb" for
+ * writing 0xbb to the register 0xaa. First move past
+ * whitespace and then begin to parse the register.
+ */
+ while ((i < buf_size) && (buf[i] == ' '))
+ i++;
+ regp = i;
+
+ /*
+ * Advance pointer to end of string then terminate
+ * the register string. This is needed to satisfy
+ * the strict_strtoul() function.
+ */
+ while ((i < buf_size) && (buf[i] != ' '))
+ i++;
+ buf[i] = '\0';
+
+ err = strict_strtoul(&buf[regp], 16, &user_reg);
+ if (err)
+ return err;
+ if (user_reg > 0xff)
+ return -EINVAL;
+
+ /* Either we read or we write a register here */
+ if (!priv->mode) {
+ /* Reading */
+ u8 reg = (u8) user_reg;
+ u8 regvalue;
+
+ ab3100_get_register(ab3100, reg, ®value);
+
+ dev_info(ab3100->dev,
+ "debug read AB3100 reg[0x%02x]: 0x%02x\n",
+ reg, regvalue);
+ } else {
+ int valp;
+ unsigned long user_value;
+ u8 reg = (u8) user_reg;
+ u8 value;
+ u8 regvalue;
+
+ /*
+ * Writing, we need some value to write to
+ * the register so keep parsing the string
+ * from userspace.
+ */
+ i++;
+ while ((i < buf_size) && (buf[i] == ' '))
+ i++;
+ valp = i;
+ while ((i < buf_size) && (buf[i] != ' '))
+ i++;
+ buf[i] = '\0';
+
+ err = strict_strtoul(&buf[valp], 16, &user_value);
+ if (err)
+ return err;
+ if (user_reg > 0xff)
+ return -EINVAL;
+
+ value = (u8) user_value;
+ ab3100_set_register(ab3100, reg, value);
+ ab3100_get_register(ab3100, reg, ®value);
+
+ dev_info(ab3100->dev,
+ "debug write reg[0x%02x] with 0x%02x, "
+ "after readback: 0x%02x\n",
+ reg, value, regvalue);
+ }
+ return buf_size;
+}
+
+static const struct file_operations ab3100_get_set_reg_fops = {
+ .open = ab3100_get_set_reg_open_file,
+ .write = ab3100_get_set_reg,
+};
+
+static struct dentry *ab3100_dir;
+static struct dentry *ab3100_reg_file;
+static struct ab3100_get_set_reg_priv ab3100_get_priv;
+static struct dentry *ab3100_get_reg_file;
+static struct ab3100_get_set_reg_priv ab3100_set_priv;
+static struct dentry *ab3100_set_reg_file;
+
+static void ab3100_setup_debugfs(struct ab3100 *ab3100)
+{
+ int err;
+
+ ab3100_dir = debugfs_create_dir("ab3100", NULL);
+ if (!ab3100_dir)
+ goto exit_no_debugfs;
+
+ ab3100_reg_file = debugfs_create_file("registers",
+ S_IRUGO, ab3100_dir, ab3100,
+ &ab3100_registers_fops);
+ if (!ab3100_reg_file) {
+ err = -ENOMEM;
+ goto exit_destroy_dir;
+ }
+
+ ab3100_get_priv.ab3100 = ab3100;
+ ab3100_get_priv.mode = false;
+ ab3100_get_reg_file = debugfs_create_file("get_reg",
+ S_IWUGO, ab3100_dir, &ab3100_get_priv,
+ &ab3100_get_set_reg_fops);
+ if (!ab3100_get_reg_file) {
+ err = -ENOMEM;
+ goto exit_destroy_reg;
+ }
+
+ ab3100_set_priv.ab3100 = ab3100;
+ ab3100_set_priv.mode = true;
+ ab3100_set_reg_file = debugfs_create_file("set_reg",
+ S_IWUGO, ab3100_dir, &ab3100_set_priv,
+ &ab3100_get_set_reg_fops);
+ if (!ab3100_set_reg_file) {
+ err = -ENOMEM;
+ goto exit_destroy_get_reg;
+ }
+ return;
+
+ exit_destroy_get_reg:
+ debugfs_remove(ab3100_get_reg_file);
+ exit_destroy_reg:
+ debugfs_remove(ab3100_reg_file);
+ exit_destroy_dir:
+ debugfs_remove(ab3100_dir);
+ exit_no_debugfs:
+ return;
+}
+static inline void ab3100_remove_debugfs(void)
+{
+ debugfs_remove(ab3100_set_reg_file);
+ debugfs_remove(ab3100_get_reg_file);
+ debugfs_remove(ab3100_reg_file);
+ debugfs_remove(ab3100_dir);
+}
+#else
+static inline void ab3100_setup_debugfs(struct ab3100 *ab3100)
+{
+}
+static inline void ab3100_remove_debugfs(void)
+{
+}
+#endif
+
+/*
+ * Basic set-up, datastructure creation/destruction and I2C interface.
+ * This sets up a default config in the AB3100 chip so that it
+ * will work as expected.
+ */
+
+struct ab3100_init_setting {
+ u8 abreg;
+ u8 setting;
+};
+
+static const struct ab3100_init_setting __initdata
+ab3100_init_settings[] = {
+ {
+ .abreg = AB3100_MCA,
+ .setting = 0x01
+ }, {
+ .abreg = AB3100_MCB,
+ .setting = 0x30
+ }, {
+ .abreg = AB3100_IMRA1,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_IMRA2,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_IMRA3,
+ .setting = 0x01
+ }, {
+ .abreg = AB3100_IMRB1,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_IMRB2,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_IMRB3,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_SUP,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_DIS,
+ .setting = 0xF0
+ }, {
+ .abreg = AB3100_D0C,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_D1C,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_D2C,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_D3C,
+ .setting = 0x00
+ },
+};
+
+static int __init ab3100_setup(struct ab3100 *ab3100)
+{
+ int err = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ab3100_init_settings); i++) {
+ err = ab3100_set_register(ab3100,
+ ab3100_init_settings[i].abreg,
+ ab3100_init_settings[i].setting);
+ if (err)
+ goto exit_no_setup;
+ }
+
+ /*
+ * Special trick to make the AB3100 use the 32kHz clock (RTC)
+ * bit 3 in test registe 0x02 is a special, undocumented test
+ * register bit that only exist in AB3100 P1E
+ */
+ if (ab3100->chip_id == 0xc4) {
+ dev_warn(ab3100->dev,
+ "AB3100 P1E variant detected, "
+ "forcing chip to 32KHz\n");
+ err = ab3100_set_test_register(ab3100, 0x02, 0x08);
+ }
+
+ exit_no_setup:
+ return err;
+}
+
+/*
+ * Here we define all the platform devices that appear
+ * as children of the AB3100. These are regular platform
+ * devices with the IORESOURCE_IO .start and .end set
+ * to correspond to the internal AB3100 register range
+ * mapping to the corresponding subdevice.
+ */
+
+#define AB3100_DEVICE(devname, devid) \
+static struct platform_device ab3100_##devname##_device = { \
+ .name = devid, \
+ .id = -1, \
+}
+
+/*
+ * This lists all the subdevices and corresponding register
+ * ranges.
+ */
+AB3100_DEVICE(dac, "ab3100-dac");
+AB3100_DEVICE(leds, "ab3100-leds");
+AB3100_DEVICE(power, "ab3100-power");
+AB3100_DEVICE(regulators, "ab3100-regulators");
+AB3100_DEVICE(sim, "ab3100-sim");
+AB3100_DEVICE(uart, "ab3100-uart");
+AB3100_DEVICE(rtc, "ab3100-rtc");
+AB3100_DEVICE(charger, "ab3100-charger");
+AB3100_DEVICE(boost, "ab3100-boost");
+AB3100_DEVICE(adc, "ab3100-adc");
+AB3100_DEVICE(fuelgauge, "ab3100-fuelgauge");
+AB3100_DEVICE(vibrator, "ab3100-vibrator");
+AB3100_DEVICE(otp, "ab3100-otp");
+AB3100_DEVICE(codec, "ab3100-codec");
+
+static struct platform_device *
+ab3100_platform_devs[] = {
+ &ab3100_dac_device,
+ &ab3100_leds_device,
+ &ab3100_power_device,
+ &ab3100_regulators_device,
+ &ab3100_sim_device,
+ &ab3100_uart_device,
+ &ab3100_rtc_device,
+ &ab3100_charger_device,
+ &ab3100_boost_device,
+ &ab3100_adc_device,
+ &ab3100_fuelgauge_device,
+ &ab3100_vibrator_device,
+ &ab3100_otp_device,
+ &ab3100_codec_device,
+};
+
+struct ab_family_id {
+ u8 id;
+ char *name;
+};
+
+static const struct ab_family_id ids[] __initdata = {
+ /* AB3100 */
+ {
+ .id = 0xc0,
+ .name = "P1A"
+ }, {
+ .id = 0xc1,
+ .name = "P1B"
+ }, {
+ .id = 0xc2,
+ .name = "P1C"
+ }, {
+ .id = 0xc3,
+ .name = "P1D"
+ }, {
+ .id = 0xc4,
+ .name = "P1E"
+ }, {
+ .id = 0xc5,
+ .name = "P1F/R1A"
+ }, {
+ .id = 0xc6,
+ .name = "P1G/R1A"
+ }, {
+ .id = 0xc7,
+ .name = "P2A/R2A"
+ }, {
+ .id = 0xc8,
+ .name = "P2B/R2B"
+ },
+ /* AB3000 variants, not supported */
+ {
+ .id = 0xa0
+ }, {
+ .id = 0xa1
+ }, {
+ .id = 0xa2
+ }, {
+ .id = 0xa3
+ }, {
+ .id = 0xa4
+ }, {
+ .id = 0xa5
+ }, {
+ .id = 0xa6
+ }, {
+ .id = 0xa7
+ },
+ /* Terminator */
+ {
+ .id = 0x00,
+ },
+};
+
+static int __init ab3100_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct ab3100 *ab3100;
+ int err;
+ int i;
+
+ ab3100 = kzalloc(sizeof(struct ab3100), GFP_KERNEL);
+ if (!ab3100) {
+ dev_err(&client->dev, "could not allocate AB3100 device\n");
+ return -ENOMEM;
+ }
+
+ /* Initialize data structure */
+ mutex_init(&ab3100->access_mutex);
+ BLOCKING_INIT_NOTIFIER_HEAD(&ab3100->event_subscribers);
+
+ ab3100->i2c_client = client;
+ ab3100->dev = &ab3100->i2c_client->dev;
+
+ i2c_set_clientdata(client, ab3100);
+
+ /* Read chip ID register */
+ err = ab3100_get_register(ab3100, AB3100_CID,
+ &ab3100->chip_id);
+ if (err) {
+ dev_err(&client->dev,
+ "could not communicate with the AB3100 analog "
+ "baseband chip\n");
+ goto exit_no_detect;
+ }
+
+ for (i = 0; ids[i].id != 0x0; i++) {
+ if (ids[i].id == ab3100->chip_id) {
+ if (ids[i].name != NULL) {
+ snprintf(&ab3100->chip_name[0],
+ sizeof(ab3100->chip_name) - 1,
+ "AB3100 %s",
+ ids[i].name);
+ break;
+ } else {
+ dev_err(&client->dev,
+ "AB3000 is not supported\n");
+ goto exit_no_detect;
+ }
+ }
+ }
+
+ if (ids[i].id == 0x0) {
+ dev_err(&client->dev, "unknown analog baseband chip id: 0x%x\n",
+ ab3100->chip_id);
+ dev_err(&client->dev, "accepting it anyway. Please update "
+ "the driver.\n");
+ goto exit_no_detect;
+ }
+
+ dev_info(&client->dev, "Detected chip: %s\n",
+ &ab3100->chip_name[0]);
+
+ /* Attach a second dummy i2c_client to the test register address */
+ ab3100->testreg_client = i2c_new_dummy(client->adapter,
+ client->addr + 1);
+ if (!ab3100->testreg_client) {
+ err = -ENOMEM;
+ goto exit_no_testreg_client;
+ }
+
+ strlcpy(ab3100->testreg_client->name, id->name,
+ sizeof(ab3100->testreg_client->name));
+
+ err = ab3100_setup(ab3100);
+ if (err)
+ goto exit_no_setup;
+
+ INIT_WORK(&ab3100->work, ab3100_work);
+
+ /* This real unpredictable IRQ is of course sampled for entropy */
+ err = request_irq(client->irq, ab3100_irq_handler,
+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+ "AB3100 IRQ", ab3100);
+ if (err)
+ goto exit_no_irq;
+
+ /* Set parent and a pointer back to the container in device data */
+ for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++) {
+ ab3100_platform_devs[i]->dev.parent =
+ &client->dev;
+ platform_set_drvdata(ab3100_platform_devs[i], ab3100);
+ }
+
+ /* Register the platform devices */
+ platform_add_devices(ab3100_platform_devs,
+ ARRAY_SIZE(ab3100_platform_devs));
+
+ ab3100_setup_debugfs(ab3100);
+
+ return 0;
+
+ exit_no_irq:
+ exit_no_setup:
+ i2c_unregister_device(ab3100->testreg_client);
+ exit_no_testreg_client:
+ exit_no_detect:
+ kfree(ab3100);
+ return err;
+}
+
+static int __exit ab3100_remove(struct i2c_client *client)
+{
+ struct ab3100 *ab3100 = i2c_get_clientdata(client);
+ int i;
+
+ /* Unregister subdevices */
+ for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++)
+ platform_device_unregister(ab3100_platform_devs[i]);
+
+ ab3100_remove_debugfs();
+ i2c_unregister_device(ab3100->testreg_client);
+
+ /*
+ * At this point, all subscribers should have unregistered
+ * their notifiers so deactivate IRQ
+ */
+ free_irq(client->irq, ab3100);
+ kfree(ab3100);
+ return 0;
+}
+
+static const struct i2c_device_id ab3100_id[] = {
+ { "ab3100", ab3100 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, ab3100_id);
+
+static struct i2c_driver ab3100_driver = {
+ .driver = {
+ .name = "ab3100",
+ .owner = THIS_MODULE,
+ },
+ .id_table = ab3100_id,
+ .probe = ab3100_probe,
+ .remove = __exit_p(ab3100_remove),
+};
+
+static int __init ab3100_i2c_init(void)
+{
+ return i2c_add_driver(&ab3100_driver);
+}
+
+static void __exit ab3100_i2c_exit(void)
+{
+ i2c_del_driver(&ab3100_driver);
+}
+
+subsys_initcall(ab3100_i2c_init);
+module_exit(ab3100_i2c_exit);
+
+MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
+MODULE_DESCRIPTION("AB3100 core driver");
+MODULE_LICENSE("GPL");
*/
#include <linux/kernel.h>
+#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/mfd/asic3.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/ds1wm.h>
+#include <linux/mfd/tmio.h>
+
+enum {
+ ASIC3_CLOCK_SPI,
+ ASIC3_CLOCK_OWM,
+ ASIC3_CLOCK_PWM0,
+ ASIC3_CLOCK_PWM1,
+ ASIC3_CLOCK_LED0,
+ ASIC3_CLOCK_LED1,
+ ASIC3_CLOCK_LED2,
+ ASIC3_CLOCK_SD_HOST,
+ ASIC3_CLOCK_SD_BUS,
+ ASIC3_CLOCK_SMBUS,
+ ASIC3_CLOCK_EX0,
+ ASIC3_CLOCK_EX1,
+};
+
+struct asic3_clk {
+ int enabled;
+ unsigned int cdex;
+ unsigned long rate;
+};
+
+#define INIT_CDEX(_name, _rate) \
+ [ASIC3_CLOCK_##_name] = { \
+ .cdex = CLOCK_CDEX_##_name, \
+ .rate = _rate, \
+ }
+
+struct asic3_clk asic3_clk_init[] __initdata = {
+ INIT_CDEX(SPI, 0),
+ INIT_CDEX(OWM, 5000000),
+ INIT_CDEX(PWM0, 0),
+ INIT_CDEX(PWM1, 0),
+ INIT_CDEX(LED0, 0),
+ INIT_CDEX(LED1, 0),
+ INIT_CDEX(LED2, 0),
+ INIT_CDEX(SD_HOST, 24576000),
+ INIT_CDEX(SD_BUS, 12288000),
+ INIT_CDEX(SMBUS, 0),
+ INIT_CDEX(EX0, 32768),
+ INIT_CDEX(EX1, 24576000),
+};
struct asic3 {
void __iomem *mapping;
u16 irq_bothedge[4];
struct gpio_chip gpio;
struct device *dev;
+
+ struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
};
static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
(reg >> asic->bus_shift));
}
+void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
+{
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&asic->lock, flags);
+ val = asic3_read_register(asic, reg);
+ if (set)
+ val |= bits;
+ else
+ val &= ~bits;
+ asic3_write_register(asic, reg, val);
+ spin_unlock_irqrestore(&asic->lock, flags);
+}
+
/* IRQs */
#define MAX_ASIC_ISR_LOOPS 20
#define ASIC3_GPIO_BASE_INCR \
return gpiochip_remove(&asic->gpio);
}
+static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
+{
+ unsigned long flags;
+ u32 cdex;
+
+ spin_lock_irqsave(&asic->lock, flags);
+ if (clk->enabled++ == 0) {
+ cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
+ cdex |= clk->cdex;
+ asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
+ }
+ spin_unlock_irqrestore(&asic->lock, flags);
+
+ return 0;
+}
+
+static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
+{
+ unsigned long flags;
+ u32 cdex;
+
+ WARN_ON(clk->enabled == 0);
+
+ spin_lock_irqsave(&asic->lock, flags);
+ if (--clk->enabled == 0) {
+ cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
+ cdex &= ~clk->cdex;
+ asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
+ }
+ spin_unlock_irqrestore(&asic->lock, flags);
+}
+
+/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
+static struct ds1wm_driver_data ds1wm_pdata = {
+ .active_high = 1,
+};
+
+static struct resource ds1wm_resources[] = {
+ {
+ .start = ASIC3_OWM_BASE,
+ .end = ASIC3_OWM_BASE + 0x13,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = ASIC3_IRQ_OWM,
+ .start = ASIC3_IRQ_OWM,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+ },
+};
+
+static int ds1wm_enable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ /* Turn on external clocks and the OWM clock */
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
+ msleep(1);
+
+ /* Reset and enable DS1WM */
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
+ ASIC3_EXTCF_OWM_RESET, 1);
+ msleep(1);
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
+ ASIC3_EXTCF_OWM_RESET, 0);
+ msleep(1);
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_OWM_EN, 1);
+ msleep(1);
+
+ return 0;
+}
+
+static int ds1wm_disable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_OWM_EN, 0);
+
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+
+ return 0;
+}
+
+static struct mfd_cell asic3_cell_ds1wm = {
+ .name = "ds1wm",
+ .enable = ds1wm_enable,
+ .disable = ds1wm_disable,
+ .driver_data = &ds1wm_pdata,
+ .num_resources = ARRAY_SIZE(ds1wm_resources),
+ .resources = ds1wm_resources,
+};
+
+static struct tmio_mmc_data asic3_mmc_data = {
+ .hclk = 24576000,
+};
+
+static struct resource asic3_mmc_resources[] = {
+ {
+ .start = ASIC3_SD_CTRL_BASE,
+ .end = ASIC3_SD_CTRL_BASE + 0x3ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = ASIC3_SD_CONFIG_BASE,
+ .end = ASIC3_SD_CONFIG_BASE + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static int asic3_mmc_enable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ /* Not sure if it must be done bit by bit, but leaving as-is */
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_LEVCD, 1);
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_LEVWP, 1);
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_SUSPEND, 0);
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_PCLR, 0);
+
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ /* CLK32 used for card detection and for interruption detection
+ * when HCLK is stopped.
+ */
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+ msleep(1);
+
+ /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
+ asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
+ CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
+
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
+ msleep(1);
+
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_SD_MEM_ENABLE, 1);
+
+ /* Enable SD card slot 3.3V power supply */
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_SDPWR, 1);
+
+ return 0;
+}
+
+static int asic3_mmc_disable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ /* Put in suspend mode */
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_SUSPEND, 1);
+
+ /* Disable clocks */
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+ return 0;
+}
+
+static struct mfd_cell asic3_cell_mmc = {
+ .name = "tmio-mmc",
+ .enable = asic3_mmc_enable,
+ .disable = asic3_mmc_disable,
+ .driver_data = &asic3_mmc_data,
+ .num_resources = ARRAY_SIZE(asic3_mmc_resources),
+ .resources = asic3_mmc_resources,
+};
+
+static int __init asic3_mfd_probe(struct platform_device *pdev,
+ struct resource *mem)
+{
+ struct asic3 *asic = platform_get_drvdata(pdev);
+ struct resource *mem_sdio;
+ int irq, ret;
+
+ mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!mem_sdio)
+ dev_dbg(asic->dev, "no SDIO MEM resource\n");
+
+ irq = platform_get_irq(pdev, 1);
+ if (irq < 0)
+ dev_dbg(asic->dev, "no SDIO IRQ resource\n");
+
+ /* DS1WM */
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_OWM_SMB, 0);
+
+ ds1wm_resources[0].start >>= asic->bus_shift;
+ ds1wm_resources[0].end >>= asic->bus_shift;
+
+ asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm;
+ asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm);
+
+ /* MMC */
+ asic3_mmc_resources[0].start >>= asic->bus_shift;
+ asic3_mmc_resources[0].end >>= asic->bus_shift;
+ asic3_mmc_resources[1].start >>= asic->bus_shift;
+ asic3_mmc_resources[1].end >>= asic->bus_shift;
+
+ asic3_cell_mmc.platform_data = &asic3_cell_mmc;
+ asic3_cell_mmc.data_size = sizeof(asic3_cell_mmc);
+
+ ret = mfd_add_devices(&pdev->dev, pdev->id,
+ &asic3_cell_ds1wm, 1, mem, asic->irq_base);
+ if (ret < 0)
+ goto out;
+
+ if (mem_sdio && (irq >= 0))
+ ret = mfd_add_devices(&pdev->dev, pdev->id,
+ &asic3_cell_mmc, 1, mem_sdio, irq);
+
+ out:
+ return ret;
+}
+
+static void asic3_mfd_remove(struct platform_device *pdev)
+{
+ mfd_remove_devices(&pdev->dev);
+}
/* Core */
static int __init asic3_probe(struct platform_device *pdev)
struct asic3 *asic;
struct resource *mem;
unsigned long clksel;
- int map_size;
int ret = 0;
asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
goto out_free;
}
- map_size = mem->end - mem->start + 1;
- asic->mapping = ioremap(mem->start, map_size);
+ asic->mapping = ioremap(mem->start, resource_size(mem));
if (!asic->mapping) {
ret = -ENOMEM;
dev_err(asic->dev, "Couldn't ioremap\n");
asic->irq_base = pdata->irq_base;
/* calculate bus shift from mem resource */
- asic->bus_shift = 2 - (map_size >> 12);
+ asic->bus_shift = 2 - (resource_size(mem) >> 12);
clksel = 0;
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
goto out_irq;
}
+ /* Making a per-device copy is only needed for the
+ * theoretical case of multiple ASIC3s on one board:
+ */
+ memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
+
+ asic3_mfd_probe(pdev, mem);
+
dev_info(asic->dev, "ASIC3 Core driver\n");
return 0;
int ret;
struct asic3 *asic = platform_get_drvdata(pdev);
+ asic3_mfd_remove(pdev);
+
ret = asic3_gpio_remove(pdev);
if (ret < 0)
return ret;
{
return i2c_add_driver(&da903x_driver);
}
-module_init(da903x_init);
+subsys_initcall(da903x_init);
static void __exit da903x_exit(void)
{
--- /dev/null
+/*
+ * Driver for Motorola PCAP2 as present in EZX phones
+ *
+ * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
+ * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mfd/ezx-pcap.h>
+#include <linux/spi/spi.h>
+
+#define PCAP_ADC_MAXQ 8
+struct pcap_adc_request {
+ u8 bank;
+ u8 ch[2];
+ u32 flags;
+ void (*callback)(void *, u16[]);
+ void *data;
+};
+
+struct pcap_adc_sync_request {
+ u16 res[2];
+ struct completion completion;
+};
+
+struct pcap_chip {
+ struct spi_device *spi;
+
+ /* IO */
+ u32 buf;
+ struct mutex io_mutex;
+
+ /* IRQ */
+ unsigned int irq_base;
+ u32 msr;
+ struct work_struct isr_work;
+ struct work_struct msr_work;
+ struct workqueue_struct *workqueue;
+
+ /* ADC */
+ struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
+ u8 adc_head;
+ u8 adc_tail;
+ struct mutex adc_mutex;
+};
+
+/* IO */
+static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
+{
+ struct spi_transfer t;
+ struct spi_message m;
+ int status;
+
+ memset(&t, 0, sizeof t);
+ spi_message_init(&m);
+ t.len = sizeof(u32);
+ spi_message_add_tail(&t, &m);
+
+ pcap->buf = *data;
+ t.tx_buf = (u8 *) &pcap->buf;
+ t.rx_buf = (u8 *) &pcap->buf;
+ status = spi_sync(pcap->spi, &m);
+
+ if (status == 0)
+ *data = pcap->buf;
+
+ return status;
+}
+
+int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
+{
+ int ret;
+
+ mutex_lock(&pcap->io_mutex);
+ value &= PCAP_REGISTER_VALUE_MASK;
+ value |= PCAP_REGISTER_WRITE_OP_BIT
+ | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
+ ret = ezx_pcap_putget(pcap, &value);
+ mutex_unlock(&pcap->io_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ezx_pcap_write);
+
+int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
+{
+ int ret;
+
+ mutex_lock(&pcap->io_mutex);
+ *value = PCAP_REGISTER_READ_OP_BIT
+ | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
+
+ ret = ezx_pcap_putget(pcap, value);
+ mutex_unlock(&pcap->io_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ezx_pcap_read);
+
+/* IRQ */
+static inline unsigned int irq2pcap(struct pcap_chip *pcap, int irq)
+{
+ return 1 << (irq - pcap->irq_base);
+}
+
+int pcap_to_irq(struct pcap_chip *pcap, int irq)
+{
+ return pcap->irq_base + irq;
+}
+EXPORT_SYMBOL_GPL(pcap_to_irq);
+
+static void pcap_mask_irq(unsigned int irq)
+{
+ struct pcap_chip *pcap = get_irq_chip_data(irq);
+
+ pcap->msr |= irq2pcap(pcap, irq);
+ queue_work(pcap->workqueue, &pcap->msr_work);
+}
+
+static void pcap_unmask_irq(unsigned int irq)
+{
+ struct pcap_chip *pcap = get_irq_chip_data(irq);
+
+ pcap->msr &= ~irq2pcap(pcap, irq);
+ queue_work(pcap->workqueue, &pcap->msr_work);
+}
+
+static struct irq_chip pcap_irq_chip = {
+ .name = "pcap",
+ .mask = pcap_mask_irq,
+ .unmask = pcap_unmask_irq,
+};
+
+static void pcap_msr_work(struct work_struct *work)
+{
+ struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
+
+ ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
+}
+
+static void pcap_isr_work(struct work_struct *work)
+{
+ struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
+ struct pcap_platform_data *pdata = pcap->spi->dev.platform_data;
+ u32 msr, isr, int_sel, service;
+ int irq;
+
+ ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
+ ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
+
+ /* We cant service/ack irqs that are assigned to port 2 */
+ if (!(pdata->config & PCAP_SECOND_PORT)) {
+ ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
+ isr &= ~int_sel;
+ }
+ ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
+
+ local_irq_disable();
+ service = isr & ~msr;
+
+ for (irq = pcap->irq_base; service; service >>= 1, irq++) {
+ if (service & 1) {
+ struct irq_desc *desc = irq_to_desc(irq);
+
+ if (WARN(!desc, KERN_WARNING
+ "Invalid PCAP IRQ %d\n", irq))
+ break;
+
+ if (desc->status & IRQ_DISABLED)
+ note_interrupt(irq, desc, IRQ_NONE);
+ else
+ desc->handle_irq(irq, desc);
+ }
+ }
+ local_irq_enable();
+}
+
+static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct pcap_chip *pcap = get_irq_data(irq);
+
+ desc->chip->ack(irq);
+ queue_work(pcap->workqueue, &pcap->isr_work);
+ return;
+}
+
+/* ADC */
+static void pcap_disable_adc(struct pcap_chip *pcap)
+{
+ u32 tmp;
+
+ ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
+ tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
+ ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
+}
+
+static void pcap_adc_trigger(struct pcap_chip *pcap)
+{
+ u32 tmp;
+ u8 head;
+
+ mutex_lock(&pcap->adc_mutex);
+ head = pcap->adc_head;
+ if (!pcap->adc_queue[head]) {
+ /* queue is empty, save power */
+ pcap_disable_adc(pcap);
+ mutex_unlock(&pcap->adc_mutex);
+ return;
+ }
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* start conversion on requested bank */
+ tmp = pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
+
+ if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
+ tmp |= PCAP_ADC_AD_SEL1;
+
+ ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
+ ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
+}
+
+static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
+{
+ struct pcap_chip *pcap = _pcap;
+ struct pcap_adc_request *req;
+ u16 res[2];
+ u32 tmp;
+
+ mutex_lock(&pcap->adc_mutex);
+ req = pcap->adc_queue[pcap->adc_head];
+
+ if (WARN(!req, KERN_WARNING "adc irq without pending request\n"))
+ return IRQ_HANDLED;
+
+ /* read requested channels results */
+ ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
+ tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
+ tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
+ tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
+ ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
+ ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
+ res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
+ res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
+
+ pcap->adc_queue[pcap->adc_head] = NULL;
+ pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* pass the results and release memory */
+ req->callback(req->data, res);
+ kfree(req);
+
+ /* trigger next conversion (if any) on queue */
+ pcap_adc_trigger(pcap);
+
+ return IRQ_HANDLED;
+}
+
+int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
+ void *callback, void *data)
+{
+ struct pcap_adc_request *req;
+
+ /* This will be freed after we have a result */
+ req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->bank = bank;
+ req->flags = flags;
+ req->ch[0] = ch[0];
+ req->ch[1] = ch[1];
+ req->callback = callback;
+ req->data = data;
+
+ mutex_lock(&pcap->adc_mutex);
+ if (pcap->adc_queue[pcap->adc_tail]) {
+ mutex_unlock(&pcap->adc_mutex);
+ kfree(req);
+ return -EBUSY;
+ }
+ pcap->adc_queue[pcap->adc_tail] = req;
+ pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* start conversion */
+ pcap_adc_trigger(pcap);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcap_adc_async);
+
+static void pcap_adc_sync_cb(void *param, u16 res[])
+{
+ struct pcap_adc_sync_request *req = param;
+
+ req->res[0] = res[0];
+ req->res[1] = res[1];
+ complete(&req->completion);
+}
+
+int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
+ u16 res[])
+{
+ struct pcap_adc_sync_request sync_data;
+ int ret;
+
+ init_completion(&sync_data.completion);
+ ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
+ &sync_data);
+ if (ret)
+ return ret;
+ wait_for_completion(&sync_data.completion);
+ res[0] = sync_data.res[0];
+ res[1] = sync_data.res[1];
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcap_adc_sync);
+
+/* subdevs */
+static int pcap_remove_subdev(struct device *dev, void *unused)
+{
+ platform_device_unregister(to_platform_device(dev));
+ return 0;
+}
+
+static int __devinit pcap_add_subdev(struct pcap_chip *pcap,
+ struct pcap_subdev *subdev)
+{
+ struct platform_device *pdev;
+
+ pdev = platform_device_alloc(subdev->name, subdev->id);
+ pdev->dev.parent = &pcap->spi->dev;
+ pdev->dev.platform_data = subdev->platform_data;
+ platform_set_drvdata(pdev, pcap);
+
+ return platform_device_add(pdev);
+}
+
+static int __devexit ezx_pcap_remove(struct spi_device *spi)
+{
+ struct pcap_chip *pcap = dev_get_drvdata(&spi->dev);
+ struct pcap_platform_data *pdata = spi->dev.platform_data;
+ int i, adc_irq;
+
+ /* remove all registered subdevs */
+ device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
+
+ /* cleanup ADC */
+ adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
+ PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
+ free_irq(adc_irq, pcap);
+ mutex_lock(&pcap->adc_mutex);
+ for (i = 0; i < PCAP_ADC_MAXQ; i++)
+ kfree(pcap->adc_queue[i]);
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* cleanup irqchip */
+ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
+ set_irq_chip_and_handler(i, NULL, NULL);
+
+ destroy_workqueue(pcap->workqueue);
+
+ kfree(pcap);
+
+ return 0;
+}
+
+static int __devinit ezx_pcap_probe(struct spi_device *spi)
+{
+ struct pcap_platform_data *pdata = spi->dev.platform_data;
+ struct pcap_chip *pcap;
+ int i, adc_irq;
+ int ret = -ENODEV;
+
+ /* platform data is required */
+ if (!pdata)
+ goto ret;
+
+ pcap = kzalloc(sizeof(*pcap), GFP_KERNEL);
+ if (!pcap) {
+ ret = -ENOMEM;
+ goto ret;
+ }
+
+ mutex_init(&pcap->io_mutex);
+ mutex_init(&pcap->adc_mutex);
+ INIT_WORK(&pcap->isr_work, pcap_isr_work);
+ INIT_WORK(&pcap->msr_work, pcap_msr_work);
+ dev_set_drvdata(&spi->dev, pcap);
+
+ /* setup spi */
+ spi->bits_per_word = 32;
+ spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
+ ret = spi_setup(spi);
+ if (ret)
+ goto free_pcap;
+
+ pcap->spi = spi;
+
+ /* setup irq */
+ pcap->irq_base = pdata->irq_base;
+ pcap->workqueue = create_singlethread_workqueue("pcapd");
+ if (!pcap->workqueue) {
+ dev_err(&spi->dev, "cant create pcap thread\n");
+ goto free_pcap;
+ }
+
+ /* redirect interrupts to AP, except adcdone2 */
+ if (!(pdata->config & PCAP_SECOND_PORT))
+ ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
+ (1 << PCAP_IRQ_ADCDONE2));
+
+ /* setup irq chip */
+ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
+ set_irq_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
+ set_irq_chip_data(i, pcap);
+#ifdef CONFIG_ARM
+ set_irq_flags(i, IRQF_VALID);
+#else
+ set_irq_noprobe(i);
+#endif
+ }
+
+ /* mask/ack all PCAP interrupts */
+ ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
+ ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
+ pcap->msr = PCAP_MASK_ALL_INTERRUPT;
+
+ set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
+ set_irq_data(spi->irq, pcap);
+ set_irq_chained_handler(spi->irq, pcap_irq_handler);
+ set_irq_wake(spi->irq, 1);
+
+ /* ADC */
+ adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
+ PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
+
+ ret = request_irq(adc_irq, pcap_adc_irq, 0, "ADC", pcap);
+ if (ret)
+ goto free_irqchip;
+
+ /* setup subdevs */
+ for (i = 0; i < pdata->num_subdevs; i++) {
+ ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
+ if (ret)
+ goto remove_subdevs;
+ }
+
+ /* board specific quirks */
+ if (pdata->init)
+ pdata->init(pcap);
+
+ return 0;
+
+remove_subdevs:
+ device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
+/* free_adc: */
+ free_irq(adc_irq, pcap);
+free_irqchip:
+ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
+ set_irq_chip_and_handler(i, NULL, NULL);
+/* destroy_workqueue: */
+ destroy_workqueue(pcap->workqueue);
+free_pcap:
+ kfree(pcap);
+ret:
+ return ret;
+}
+
+static struct spi_driver ezxpcap_driver = {
+ .probe = ezx_pcap_probe,
+ .remove = __devexit_p(ezx_pcap_remove),
+ .driver = {
+ .name = "ezx-pcap",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init ezx_pcap_init(void)
+{
+ return spi_register_driver(&ezxpcap_driver);
+}
+
+static void __exit ezx_pcap_exit(void)
+{
+ spi_unregister_driver(&ezxpcap_driver);
+}
+
+module_init(ezx_pcap_init);
+module_exit(ezx_pcap_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
+MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
MODULE_LICENSE("GPL");
-module_init(pcf50633_init);
+subsys_initcall(pcf50633_init);
module_exit(pcf50633_exit);
*/
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/mfd/pcf50633/core.h>
#include <linux/mfd/pcf50633/gpio.h>
return pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
}
EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set);
+
+MODULE_LICENSE("GPL");
/*--------------------------------------------------------------------------*/
-static const struct tmio_mmc_data t7166xb_mmc_data = {
+static struct tmio_mmc_data t7166xb_mmc_data = {
.hclk = 24000000,
};
/*--------------------------------------------------------------------------*/
-const static struct tmio_mmc_data tc6387xb_mmc_data = {
+static struct tmio_mmc_data tc6387xb_mmc_data = {
.hclk = 24000000,
};
return 0;
}
-const static struct tmio_mmc_data tc6393xb_mmc_data = {
+static struct tmio_mmc_data tc6393xb_mmc_data = {
.hclk = 24000000,
};
return e;
}
-static void __init clocks_init(struct device *dev)
+static void clocks_init(struct device *dev)
{
int e = 0;
struct clk *osc;
* thread. All we do here is acknowledge and mask the interrupt and wakeup
* the kernel thread.
*/
-static void handle_twl4030_pih(unsigned int irq, irq_desc_t *desc)
+static void handle_twl4030_pih(unsigned int irq, struct irq_desc *desc)
{
/* Acknowledge, clear *AND* mask the interrupt... */
desc->chip->ack(irq);
/* read write volatile */
{ 0xFFFF, 0xFFFF, 0xFFFF }, /* R0 - Reset/ID */
{ 0x7CFF, 0x0C00, 0x7FFF }, /* R1 - ID */
- { 0x0000, 0x0000, 0x0000 }, /* R2 */
+ { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
{ 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
{ 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
{ 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
{ 0x0000, 0x0000, 0x0000 }, /* R224 */
{ 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */
{ 0x0000, 0x0000, 0xFFFF }, /* R226 - Charger status */
- { 0x0000, 0x0000, 0xFFFF }, /* R227 */
+ { 0x34FE, 0x0000, 0xFFFF }, /* R227 */
{ 0x0000, 0x0000, 0x0000 }, /* R228 */
{ 0x0000, 0x0000, 0x0000 }, /* R229 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R230 - GPIO Pin Status */
return ret;
}
-module_init(wm8400_module_init);
+subsys_initcall(wm8400_module_init);
static void __exit wm8400_module_exit(void)
{
--- /dev/null
+/*
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * AB3100 core access functions
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+
+#include <linux/device.h>
+
+#ifndef MFD_AB3100_H
+#define MFD_AB3100_H
+
+#define ABUNKNOWN 0
+#define AB3000 1
+#define AB3100 2
+
+/*
+ * AB3100, EVENTA1, A2 and A3 event register flags
+ * these are catenated into a single 32-bit flag in the code
+ * for event notification broadcasts.
+ */
+#define AB3100_EVENTA1_ONSWA (0x01<<16)
+#define AB3100_EVENTA1_ONSWB (0x02<<16)
+#define AB3100_EVENTA1_ONSWC (0x04<<16)
+#define AB3100_EVENTA1_DCIO (0x08<<16)
+#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
+#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
+#define AB3100_EVENTA1_VBUS (0x40<<16)
+#define AB3100_EVENTA1_VSET_USB (0x80<<16)
+
+#define AB3100_EVENTA2_READY_TX (0x01<<8)
+#define AB3100_EVENTA2_READY_RX (0x02<<8)
+#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
+#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
+#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
+#define AB3100_EVENTA2_MIDR (0x20<<8)
+#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
+#define AB3100_EVENTA2_ALARM (0x80<<8)
+
+#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
+#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
+#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
+#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
+#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
+#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
+#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
+#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
+
+/* AB3100, STR register flags */
+#define AB3100_STR_ONSWA (0x01)
+#define AB3100_STR_ONSWB (0x02)
+#define AB3100_STR_ONSWC (0x04)
+#define AB3100_STR_DCIO (0x08)
+#define AB3100_STR_BOOT_MODE (0x10)
+#define AB3100_STR_SIM_OFF (0x20)
+#define AB3100_STR_BATT_REMOVAL (0x40)
+#define AB3100_STR_VBUS (0x80)
+
+/**
+ * struct ab3100
+ * @access_mutex: lock out concurrent accesses to the AB3100 registers
+ * @dev: pointer to the containing device
+ * @i2c_client: I2C client for this chip
+ * @testreg_client: secondary client for test registers
+ * @chip_name: name of this chip variant
+ * @chip_id: 8 bit chip ID for this chip variant
+ * @work: an event handling worker
+ * @event_subscribers: event subscribers are listed here
+ * @startup_events: a copy of the first reading of the event registers
+ * @startup_events_read: whether the first events have been read
+ *
+ * This struct is PRIVATE and devices using it should NOT
+ * access ANY fields. It is used as a token for calling the
+ * AB3100 functions.
+ */
+struct ab3100 {
+ struct mutex access_mutex;
+ struct device *dev;
+ struct i2c_client *i2c_client;
+ struct i2c_client *testreg_client;
+ char chip_name[32];
+ u8 chip_id;
+ struct work_struct work;
+ struct blocking_notifier_head event_subscribers;
+ u32 startup_events;
+ bool startup_events_read;
+};
+
+int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval);
+int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval);
+int ab3100_get_register_page(struct ab3100 *ab3100,
+ u8 first_reg, u8 *regvals, u8 numregs);
+int ab3100_mask_and_set_register(struct ab3100 *ab3100,
+ u8 reg, u8 andmask, u8 ormask);
+u8 ab3100_get_chip_type(struct ab3100 *ab3100);
+int ab3100_event_register(struct ab3100 *ab3100,
+ struct notifier_block *nb);
+int ab3100_event_unregister(struct ab3100 *ab3100,
+ struct notifier_block *nb);
+int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
+ u32 *fatevent);
+
+#endif
#define ASIC3_NUM_GPIOS 64
#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
+#define ASIC3_IRQ_LED0 64
+#define ASIC3_IRQ_LED1 65
+#define ASIC3_IRQ_LED2 66
+#define ASIC3_IRQ_SPI 67
+#define ASIC3_IRQ_SMBUS 68
+#define ASIC3_IRQ_OWM 69
+
#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
#define ASIC3_GPIO_BANK_A 0
/* Basic control of the SD ASIC */
-#define ASIC3_SDHWCTRL_Base 0x0E00
-#define ASIC3_SDHWCTRL_SDConf 0x00
+#define ASIC3_SDHWCTRL_BASE 0x0E00
+#define ASIC3_SDHWCTRL_SDCONF 0x00
#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
/* SD card power supply ctrl 1=enable */
#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
-#define ASIC3_EXTCF_Base 0x1100
+#define ASIC3_EXTCF_BASE 0x1100
-#define ASIC3_EXTCF_Select 0x00
-#define ASIC3_EXTCF_Reset 0x04
+#define ASIC3_EXTCF_SELECT 0x00
+#define ASIC3_EXTCF_RESET 0x04
#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
* SDIO_CTRL Control registers for SDIO operations
*
*****************************************************************************/
-#define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */
-
-#define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */
-
-/* [0:8] SD Control Register Base Address */
-#define ASIC3_SD_CONFIG_Addr0 0x20
-
-/* [9:31] SD Control Register Base Address */
-#define ASIC3_SD_CONFIG_Addr1 0x24
-
-/* R/O: interrupt assigned to pin */
-#define ASIC3_SD_CONFIG_IntPin 0x78
-
-/*
- * Set to 0x1f to clock SD controller, 0 otherwise.
- * At 0x82 - Gated Clock Ctrl
- */
-#define ASIC3_SD_CONFIG_ClkStop 0x80
-
-/* Control clock of SD controller */
-#define ASIC3_SD_CONFIG_ClockMode 0x84
-#define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */
-#define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */
-
-/* auto power up after card inserted */
-#define ASIC3_SD_CONFIG_SDHC_Power2 0x92
-
-/* auto power down when card removed */
-#define ASIC3_SD_CONFIG_SDHC_Power3 0x94
-#define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98
-#define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */
-#define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */
-#define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/
-
-/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
-#define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8
-#define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */
-
-/* Bit 1: double buffer/single buffer */
-#define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0
-
-/* Memory access enable (set to 1 to access SD Controller) */
-#define SD_CONFIG_COMMAND_MAE (1<<1)
-
-#define SD_CONFIG_CLK_ENABLE_ALL 0x1f
-
-#define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */
-#define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */
-
- /* two bits - number of cycles for card detection */
-#define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3)
-
-
-#define ASIC3_SD_CTRL_Base 0x1000
-
-#define ASIC3_SD_CTRL_Cmd 0x00
-#define ASIC3_SD_CTRL_Arg0 0x08
-#define ASIC3_SD_CTRL_Arg1 0x0C
-#define ASIC3_SD_CTRL_StopInternal 0x10
-#define ASIC3_SD_CTRL_TransferSectorCount 0x14
-#define ASIC3_SD_CTRL_Response0 0x18
-#define ASIC3_SD_CTRL_Response1 0x1C
-#define ASIC3_SD_CTRL_Response2 0x20
-#define ASIC3_SD_CTRL_Response3 0x24
-#define ASIC3_SD_CTRL_Response4 0x28
-#define ASIC3_SD_CTRL_Response5 0x2C
-#define ASIC3_SD_CTRL_Response6 0x30
-#define ASIC3_SD_CTRL_Response7 0x34
-#define ASIC3_SD_CTRL_CardStatus 0x38
-#define ASIC3_SD_CTRL_BufferCtrl 0x3C
-#define ASIC3_SD_CTRL_IntMaskCard 0x40
-#define ASIC3_SD_CTRL_IntMaskBuffer 0x44
-#define ASIC3_SD_CTRL_CardClockCtrl 0x48
-#define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C
-#define ASIC3_SD_CTRL_MemCardOptionSetup 0x50
-#define ASIC3_SD_CTRL_ErrorStatus0 0x58
-#define ASIC3_SD_CTRL_ErrorStatus1 0x5C
-#define ASIC3_SD_CTRL_DataPort 0x60
-#define ASIC3_SD_CTRL_TransactionCtrl 0x68
-#define ASIC3_SD_CTRL_SoftwareReset 0x1C0
-
-#define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0)
-
-#define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8)
-
-#define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15)
-#define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0)
-#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0)
-
-#define MEM_CARD_OPTION_REQUIRED 0x000e
-#define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4)
-#define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14)
-#define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15)
-#define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0
-
-#define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f)
-#define SD_CTRL_COMMAND_TYPE_CMD (0 << 6)
-#define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6)
-#define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6)
-#define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8)
-#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8)
-#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8)
-#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8)
-#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8)
-#define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11)
-#define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12)
-#define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12)
-#define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13)
-#define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14)
-
-#define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0)
-#define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8)
-
-#define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0)
-#define SD_CTRL_CARDSTATUS_RW_END (1 << 2)
-#define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3)
-#define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4)
-#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5)
-#define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7)
-#define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8)
-#define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9)
-#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10)
-
-#define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0)
-#define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1)
-#define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2)
-#define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3)
-#define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4)
-#define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5)
-#define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6)
-#define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7)
-#define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8)
-#define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9)
-#define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13)
-#define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14)
-#define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15)
-
-#define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0)
-#define SD_CTRL_INTMASKCARD_RW_END (1 << 2)
-#define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3)
-#define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4)
-#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
-#define SD_CTRL_INTMASKCARD_UNK6 (1 << 6)
-#define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7)
-#define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8)
-#define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9)
-#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
-
-#define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0)
-#define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1)
-#define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2)
-#define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3)
-#define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4)
-#define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5)
-#define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6)
-#define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7)
-#define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8)
-#define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9)
-#define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13)
-#define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14)
-#define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15)
-
-#define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0)
-#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
-#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3)
-#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4)
-#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5)
-#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8)
-#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9)
-#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10)
-#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11)
-
-#define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0)
-#define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4)
-#define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5)
-#define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6)
-
-#define ASIC3_SDIO_CTRL_Base 0x1200
-
-#define ASIC3_SDIO_CTRL_Cmd 0x00
-#define ASIC3_SDIO_CTRL_CardPortSel 0x04
-#define ASIC3_SDIO_CTRL_Arg0 0x08
-#define ASIC3_SDIO_CTRL_Arg1 0x0C
-#define ASIC3_SDIO_CTRL_TransferBlockCount 0x14
-#define ASIC3_SDIO_CTRL_Response0 0x18
-#define ASIC3_SDIO_CTRL_Response1 0x1C
-#define ASIC3_SDIO_CTRL_Response2 0x20
-#define ASIC3_SDIO_CTRL_Response3 0x24
-#define ASIC3_SDIO_CTRL_Response4 0x28
-#define ASIC3_SDIO_CTRL_Response5 0x2C
-#define ASIC3_SDIO_CTRL_Response6 0x30
-#define ASIC3_SDIO_CTRL_Response7 0x34
-#define ASIC3_SDIO_CTRL_CardStatus 0x38
-#define ASIC3_SDIO_CTRL_BufferCtrl 0x3C
-#define ASIC3_SDIO_CTRL_IntMaskCard 0x40
-#define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44
-#define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C
-#define ASIC3_SDIO_CTRL_CardOptionSetup 0x50
-#define ASIC3_SDIO_CTRL_ErrorStatus0 0x54
-#define ASIC3_SDIO_CTRL_ErrorStatus1 0x58
-#define ASIC3_SDIO_CTRL_DataPort 0x60
-#define ASIC3_SDIO_CTRL_TransactionCtrl 0x68
-#define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C
-#define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70
-#define ASIC3_SDIO_CTRL_HostInformation 0x74
-#define ASIC3_SDIO_CTRL_ErrorCtrl 0x78
-#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
-#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
+#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
+#define ASIC3_SD_CTRL_BASE 0x1000
+#define ASIC3_SDIO_CTRL_BASE 0x1200
#define ASIC3_MAP_SIZE_32BIT 0x2000
#define ASIC3_MAP_SIZE_16BIT 0x1000
--- /dev/null
+/*
+ * Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
+ *
+ * For further information, please see http://wiki.openezx.org/PCAP2
+ */
+
+#ifndef EZX_PCAP_H
+#define EZX_PCAP_H
+
+struct pcap_subdev {
+ int id;
+ const char *name;
+ void *platform_data;
+};
+
+struct pcap_platform_data {
+ unsigned int irq_base;
+ unsigned int config;
+ void (*init) (void *); /* board specific init */
+ int num_subdevs;
+ struct pcap_subdev *subdevs;
+};
+
+struct pcap_chip;
+
+int ezx_pcap_write(struct pcap_chip *, u8, u32);
+int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
+int pcap_to_irq(struct pcap_chip *, int);
+int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
+int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
+
+#define PCAP_SECOND_PORT 1
+#define PCAP_CS_AH 2
+
+#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
+#define PCAP_REGISTER_READ_OP_BIT 0x00000000
+
+#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
+#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
+#define PCAP_REGISTER_ADDRESS_SHIFT 26
+#define PCAP_REGISTER_NUMBER 32
+#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
+#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
+
+/* registers acessible by both pcap ports */
+#define PCAP_REG_ISR 0x0 /* Interrupt Status */
+#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
+#define PCAP_REG_PSTAT 0x2 /* Processor Status */
+#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
+#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
+#define PCAP_REG_BATT 0x8 /* Battery Control */
+#define PCAP_REG_ADC 0x9 /* AD Control */
+#define PCAP_REG_ADR 0xa /* AD Result */
+#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
+#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
+#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
+#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
+#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
+#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
+#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
+#define PCAP_REG_GP 0x1b /* General Purpose */
+#define PCAP_REG_TEST1 0x1c
+#define PCAP_REG_TEST2 0x1d
+#define PCAP_REG_VENDOR_TEST1 0x1e
+#define PCAP_REG_VENDOR_TEST2 0x1f
+
+/* registers acessible by pcap port 1 only (a1200, e2 & e6) */
+#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
+#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
+#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
+#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
+#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
+#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
+#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
+#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
+#define PCAP_REG_PWR 0x13 /* Power Control */
+#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
+#define PCAP_REG_VENDOR_REV 0x17
+#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
+
+/* PCAP2 Interrupts */
+#define PCAP_NIRQS 23
+#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
+#define PCAP_IRQ_TS 1 /* Touch Screen */
+#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
+#define PCAP_IRQ_WH 3 /* ADC above high limit */
+#define PCAP_IRQ_WL 4 /* ADC below low limit */
+#define PCAP_IRQ_TODA 5 /* Time of day alarm */
+#define PCAP_IRQ_USB4V 6 /* USB above 4V */
+#define PCAP_IRQ_ONOFF 7 /* On/Off button */
+#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
+#define PCAP_IRQ_USB1V 9 /* USB above 1V */
+#define PCAP_IRQ_MOBPORT 10
+#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
+#define PCAP_IRQ_HS 12 /* Headset attach */
+#define PCAP_IRQ_ST 13
+#define PCAP_IRQ_PC 14 /* Power Cut */
+#define PCAP_IRQ_WARM 15
+#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
+#define PCAP_IRQ_CLK 17
+#define PCAP_IRQ_SYSRST 18 /* System Reset */
+#define PCAP_IRQ_DUMMY 19
+#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
+#define PCAP_IRQ_SOFTRESET 21
+#define PCAP_IRQ_MNEXB 22
+
+/* voltage regulators */
+#define V1 0
+#define V2 1
+#define V3 2
+#define V4 3
+#define V5 4
+#define V6 5
+#define V7 6
+#define V8 7
+#define V9 8
+#define V10 9
+#define VAUX1 10
+#define VAUX2 11
+#define VAUX3 12
+#define VAUX4 13
+#define VSIM 14
+#define VSIM2 15
+#define VVIB 16
+#define SW1 17
+#define SW2 18
+#define SW3 19
+#define SW1S 20
+#define SW2S 21
+
+#define PCAP_BATT_DAC_MASK 0x000000ff
+#define PCAP_BATT_DAC_SHIFT 0
+#define PCAP_BATT_B_FDBK (1 << 8)
+#define PCAP_BATT_EXT_ISENSE (1 << 9)
+#define PCAP_BATT_V_COIN_MASK 0x00003c00
+#define PCAP_BATT_V_COIN_SHIFT 10
+#define PCAP_BATT_I_COIN (1 << 14)
+#define PCAP_BATT_COIN_CH_EN (1 << 15)
+#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
+#define PCAP_BATT_EOL_SEL_SHIFT 17
+#define PCAP_BATT_EOL_CMP_EN (1 << 20)
+#define PCAP_BATT_BATT_DET_EN (1 << 21)
+#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
+
+#define PCAP_ADC_ADEN (1 << 0)
+#define PCAP_ADC_RAND (1 << 1)
+#define PCAP_ADC_AD_SEL1 (1 << 2)
+#define PCAP_ADC_AD_SEL2 (1 << 3)
+#define PCAP_ADC_ADA1_MASK 0x00000070
+#define PCAP_ADC_ADA1_SHIFT 4
+#define PCAP_ADC_ADA2_MASK 0x00000380
+#define PCAP_ADC_ADA2_SHIFT 7
+#define PCAP_ADC_ATO_MASK 0x00003c00
+#define PCAP_ADC_ATO_SHIFT 10
+#define PCAP_ADC_ATOX (1 << 14)
+#define PCAP_ADC_MTR1 (1 << 15)
+#define PCAP_ADC_MTR2 (1 << 16)
+#define PCAP_ADC_TS_M_MASK 0x000e0000
+#define PCAP_ADC_TS_M_SHIFT 17
+#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
+#define PCAP_ADC_TS_REFENB (1 << 21)
+#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
+#define PCAP_ADC_BATT_I_ADC (1 << 23)
+
+#define PCAP_ADC_BANK_0 0
+#define PCAP_ADC_BANK_1 1
+/* ADC bank 0 */
+#define PCAP_ADC_CH_COIN 0
+#define PCAP_ADC_CH_BATT 1
+#define PCAP_ADC_CH_BPLUS 2
+#define PCAP_ADC_CH_MOBPORTB 3
+#define PCAP_ADC_CH_TEMPERATURE 4
+#define PCAP_ADC_CH_CHARGER_ID 5
+#define PCAP_ADC_CH_AD6 6
+/* ADC bank 1 */
+#define PCAP_ADC_CH_AD7 0
+#define PCAP_ADC_CH_AD8 1
+#define PCAP_ADC_CH_AD9 2
+#define PCAP_ADC_CH_TS_X1 3
+#define PCAP_ADC_CH_TS_X2 4
+#define PCAP_ADC_CH_TS_Y1 5
+#define PCAP_ADC_CH_TS_Y2 6
+
+#define PCAP_ADC_T_NOW 0
+#define PCAP_ADC_T_IN_BURST 1
+#define PCAP_ADC_T_OUT_BURST 2
+
+#define PCAP_ADC_ATO_IN_BURST 6
+#define PCAP_ADC_ATO_OUT_BURST 0
+
+#define PCAP_ADC_TS_M_XY 1
+#define PCAP_ADC_TS_M_PRESSURE 2
+#define PCAP_ADC_TS_M_PLATE_X 3
+#define PCAP_ADC_TS_M_PLATE_Y 4
+#define PCAP_ADC_TS_M_STANDBY 5
+#define PCAP_ADC_TS_M_NONTS 6
+
+#define PCAP_ADR_ADD1_MASK 0x000003ff
+#define PCAP_ADR_ADD1_SHIFT 0
+#define PCAP_ADR_ADD2_MASK 0x000ffc00
+#define PCAP_ADR_ADD2_SHIFT 10
+#define PCAP_ADR_ADINC1 (1 << 20)
+#define PCAP_ADR_ADINC2 (1 << 21)
+#define PCAP_ADR_ASC (1 << 22)
+#define PCAP_ADR_ONESHOT (1 << 23)
+
+#define PCAP_BUSCTRL_FSENB (1 << 0)
+#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
+#define PCAP_BUSCTRL_USB_PU (1 << 2)
+#define PCAP_BUSCTRL_USB_PD (1 << 3)
+#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
+#define PCAP_BUSCTRL_USB_PS (1 << 5)
+#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
+#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
+#define PCAP_BUSCTRL_CURRLIM (1 << 8)
+#define PCAP_BUSCTRL_RS232ENB (1 << 9)
+#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
+#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
+#define PCAP_BUSCTRL_USB_PDM (1 << 12)
+#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
+
+/* leds */
+#define PCAP_LED0 0
+#define PCAP_LED1 1
+#define PCAP_BL0 2
+#define PCAP_BL1 3
+#define PCAP_VIB 4
+#define PCAP_LED_3MA 0
+#define PCAP_LED_4MA 1
+#define PCAP_LED_5MA 2
+#define PCAP_LED_9MA 3
+#define PCAP_LED_GPIO_VAL_MASK 0x00ffffff
+#define PCAP_LED_GPIO_EN 0x01000000
+#define PCAP_LED_GPIO_INVERT 0x02000000
+#define PCAP_LED_T_MASK 0xf
+#define PCAP_LED_C_MASK 0x3
+#define PCAP_BL_MASK 0x1f
+#define PCAP_BL0_SHIFT 0
+#define PCAP_LED0_EN (1 << 5)
+#define PCAP_LED1_EN (1 << 6)
+#define PCAP_LED0_T_SHIFT 7
+#define PCAP_LED1_T_SHIFT 11
+#define PCAP_LED0_C_SHIFT 15
+#define PCAP_LED1_C_SHIFT 17
+#define PCAP_BL1_SHIFT 20
+#define PCAP_VIB_MASK 0x3
+#define PCAP_VIB_SHIFT 20
+#define PCAP_VIB_EN (1 << 19)
+
+/* RTC */
+#define PCAP_RTC_DAY_MASK 0x3fff
+#define PCAP_RTC_TOD_MASK 0xffff
+#define PCAP_RTC_PC_MASK 0x7
+#define SEC_PER_DAY 86400
+
+#endif
* data for the MMC controller
*/
struct tmio_mmc_data {
- unsigned int hclk;
+ const unsigned int hclk;
};
/*
projects / mv-sheeva.git / commitdiff