ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for irqpin module

This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state.
By making it available to the driver, we make sure it gets enabled when
needed, and allow it to be managed by system or runtime PM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 076708797ef67b91cc9f8d9d1e701cf396608160..08f736d52179b677496c41d887479fa74371a63c 100644 (file)
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -94,6 +94,7 @@
                              0 6 IRQ_TYPE_LEVEL_HIGH
                              0 7 IRQ_TYPE_LEVEL_HIGH
                              0 8 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
                control-parent;
        };
 
@@ -114,6 +115,7 @@
                              0 14 IRQ_TYPE_LEVEL_HIGH
                              0 15 IRQ_TYPE_LEVEL_HIGH
                              0 16 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
                control-parent;
        };
 
@@ -134,6 +136,7 @@
                              0 22 IRQ_TYPE_LEVEL_HIGH
                              0 23 IRQ_TYPE_LEVEL_HIGH
                              0 24 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
                control-parent;
        };
 
@@ -154,6 +157,7 @@
                              0 30 IRQ_TYPE_LEVEL_HIGH
                              0 31 IRQ_TYPE_LEVEL_HIGH
                              0 32 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
                control-parent;
        };
 
@@ -698,5 +702,16 @@
                        clock-output-names =
                                "iic3", "iic4", "keysc";
                };
+               mstp5_clks: mstp5_clks@e6150144 {
+                       compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+                       reg = <0xe6150144 4>, <0xe615003c 4>;
+                       clocks = <&cpg_clocks SH73A0_CLK_HP>;
+                       #clock-cells = <1>;
+                       clock-indices = <
+                               SH73A0_CLK_INTCA0
+                       >;
+                       clock-output-names =
+                               "intca0";
+               };
        };
 };

diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h
index 1dd3eb2b7d902afd356f4c96aa293d0972ad8313..53369568c24c5dc6055f34c34e5babc318397d3f 100644 (file)
--- a/include/dt-bindings/clock/sh73a0-clock.h
+++ b/include/dt-bindings/clock/sh73a0-clock.h
@@ -76,4 +76,7 @@
 #define SH73A0_CLK_IIC4                10
 #define SH73A0_CLK_KEYSC       3
 
+/* MSTP5 */
+#define SH73A0_CLK_INTCA0      8
+
 #endif