Merge branch 'v3.16-next/dt-samsung' into for-next

Conflicts:
	arch/arm/mach-exynos/firmware.c

diff --cc arch/arm/Kconfig
Simple merge

diff --cc arch/arm/boot/dts/Makefile
Simple merge

diff --cc arch/arm/boot/dts/exynos4412-trats2.dts
Simple merge

diff --cc arch/arm/boot/dts/exynos5420-arndale-octa.dts
Simple merge

diff --cc arch/arm/boot/dts/exynos5420.dtsi
index edfd6110f5214b8bbbbc03e9adbfd06f926c941e,c0436b8563c36d4aceb4a32a31a818f87e1ce0ad..34e4e7e4b959eddddc2c4f7d01a83d9c8c0c3240
--- 1/arch/arm/boot/dts/exynos5420.dtsi
--- 2/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@@ -727,5 -756,58 +753,57 @@@
                interrupts = <0 112 0>;
                clocks = <&clock 471>;
                clock-names = "secss";
 -              samsung,power-domain = <&g2d_pd>;
        };
+ 
+       usbdrd3_0: usb@12000000 {
+               compatible = "samsung,exynos5250-dwusb3";
+               clocks = <&clock CLK_USBD300>;
+               clock-names = "usbdrd30";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+ 
+               dwc3 {
+                       compatible = "snps,dwc3";
+                       reg = <0x12000000 0x10000>;
+                       interrupts = <0 72 0>;
+                       phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+                       phy-names = "usb2-phy", "usb3-phy";
+               };
+       };
+ 
+       usbdrd_phy0: phy@12100000 {
+               compatible = "samsung,exynos5420-usbdrd-phy";
+               reg = <0x12100000 0x100>;
+               clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+               clock-names = "phy", "ref";
+               samsung,pmu-syscon = <&pmu_system_controller>;
+               #phy-cells = <1>;
+       };
+ 
+       usbdrd3_1: usb@12400000 {
+               compatible = "samsung,exynos5250-dwusb3";
+               clocks = <&clock CLK_USBD301>;
+               clock-names = "usbdrd30";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+ 
+               dwc3 {
+                       compatible = "snps,dwc3";
+                       reg = <0x12400000 0x10000>;
+                       interrupts = <0 73 0>;
+                       phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+                       phy-names = "usb2-phy", "usb3-phy";
+               };
+       };
+ 
+       usbdrd_phy1: phy@12500000 {
+               compatible = "samsung,exynos5420-usbdrd-phy";
+               reg = <0x12500000 0x100>;
+               clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+               clock-names = "phy", "ref";
+               samsung,pmu-syscon = <&pmu_system_controller>;
+               #phy-cells = <1>;
+       };
  };

diff --cc arch/arm/mach-exynos/common.h
Simple merge

diff --cc arch/arm/mach-exynos/exynos.c
Simple merge

diff --cc arch/arm/mach-exynos/firmware.c
index aa01c4222b40334db58a603cbcbee82f5f671d6b,483dfcd690650c54674584169b99ef00967964d0..739bdc88b651b6e1129778e77242deb4e54d4245
--- 1/arch/arm/mach-exynos/firmware.c
--- 2/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@@ -44,10 -35,12 +43,15 @@@ static int exynos_cpu_boot(int cpu
  
  static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
  {
-       void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
+       void __iomem *boot_reg;
+ 
+       if (!sysram_ns_base_addr)
+               return -ENODEV;
+ 
 -      boot_reg = sysram_ns_base_addr + 0x1c + 4*cpu;
++      boot_reg = sysram_ns_base_addr + 0x1c;
 +
 +      if (!soc_is_exynos4212())
 +              boot_reg += 4*cpu;
  
        __raw_writel(boot_addr, boot_reg);
        return 0;

diff --cc arch/arm/mach-exynos/platsmp.c
Simple merge