ARM: tegra: dt: add L2 cache controller

Add L2 cache controller binding into DT for Tegra.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f3a09d0d45bc801a012fe7ea97f73548384ae9ad..f40cfbaa7c7e3a70438570dd2dde4626191dafad 100644 (file)
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,15 @@
        compatible = "nvidia,tegra20";
        interrupt-parent = <&intc>;
 
+       cache-controller@50043000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x50043000 0x1000>;
+               arm,data-latency = <5 5 2>;
+               arm,tag-latency = <4 4 2>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b1497c7d7d6851db3753c1210e974cb9e47888c2..148371b432a0e63a6ea648a184f29944ea5eb3a9 100644 (file)
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,15 @@
        compatible = "nvidia,tegra30";
        interrupt-parent = <&intc>;
 
+       cache-controller@50043000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x50043000 0x1000>;
+               arm,data-latency = <6 6 2>;
+               arm,tag-latency = <5 5 2>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000