/System.map
/u-boot
/u-boot.hex
+/u-boot.imx
/u-boot.map
/u-boot.bin
/u-boot.srec
MIP405 PPC4xx
PIP405 PPC4xx
+Werner Pfister <Pfister_Werner@intercontrol.de>
+ digsy_mtc mpc5200
+ digsy_mtc_rev5 mpc5200
+
Kim Phillips <kim.phillips@freescale.com>
MPC8349EMDS MPC8349
ids8247 MPC8247
jupiter MPC5200
kmeter1 MPC8360
- kmsupx4 MPC852T
mgcoge MPC8247
- mgsuvd MPC852
mucmc52 MPC5200
muas3001 MPC8270
municse MPC5200
%_config:: unconfig
@$(MKCONFIG) -A $(@:_config=)
-sinclude .boards.depend
-.boards.depend: boards.cfg
+sinclude $(obj).boards.depend
+$(obj).boards.depend: boards.cfg
awk '(NF && $$1 !~ /^#/) { print $$1 ": " $$1 "_config; $$(MAKE)" }' $< > $@
#
@rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
- @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+ @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
(requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR Support for DCR Register access
(4xx only)
- CONFIG_CMD_SHA1 print sha1 memory digest
+ CONFIG_CMD_SHA1SUM print sha1 memory digest
(requires CONFIG_CMD_MEMORY)
CONFIG_CMD_SOURCE "source" command Support
CONFIG_CMD_SPI * SPI serial bus support
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#if !defined(CONFIG_SYS_NO_FLASH)
- puts ("FLASH: ");
+ puts ("Flash: ");
if ((flash_size = flash_init ()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
malloc_bin_reloc ();
#if !defined(CONFIG_SYS_NO_FLASH)
- puts ("FLASH: ");
+ puts ("Flash: ");
if ((flash_size = flash_init ()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
printf ("\tU-Boot Start:0x%08x\n", CONFIG_SYS_TEXT_BASE);
#if defined(CONFIG_CMD_FLASH)
- puts ("FLASH: ");
+ puts ("Flash: ");
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
if (0 < (flash_size = flash_init ())) {
bd->bi_flashsize = flash_size;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#if !defined(CONFIG_SYS_NO_FLASH)
- puts ("FLASH: ");
+ puts ("Flash: ");
if (board_flash_wp_on()) {
printf("Uninitialized - Write Protect On\n");
gd->bd->bi_flashsize = flash_init();
if (gd->bd->bi_flashsize >= (1024 * 1024))
- printf("FLASH: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
+ printf("Flash: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
else
- printf("FLASH: %ldKB\n", gd->bd->bi_flashsize / 1024);
+ printf("Flash: %ldKB\n", gd->bd->bi_flashsize / 1024);
return 0;
}
malloc_bin_reloc();
#if !defined(CONFIG_SYS_NO_FLASH)
- puts("FLASH: ");
+ puts("Flash: ");
if ((flash_size = flash_init()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
#include <asm/processor.h>
#include <asm/io.h>
#include "eeprom.h"
+#if defined(CONFIG_DIGSY_REV5)
+#include "is45s16800a2.h"
+#include <mtd/cfi_flash.h>
+#else
#include "is42s16800a-7t.h"
+#endif
+#include <libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
extern int usb_cpu_init(void);
+#if defined(CONFIG_DIGSY_REV5)
+/*
+ * The M29W128GH needs a specail reset command function,
+ * details see the doc/README.cfi file
+ */
+void flash_cmd_reset(flash_info_t *info)
+{
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+}
+#endif
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
char *s = getenv("serial#");
puts ("Board: InterControl digsyMTC");
+#if defined(CONFIG_DIGSY_REV5)
+ puts (" rev5");
+#endif
if (s != NULL) {
puts(", ");
puts(s);
setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
}
#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_CMD_IDE */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+static void ft_delete_node(void *fdt, const char *compat)
+{
+ int off = -1;
+ int ret;
+
+ off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ if (off < 0) {
+ printf("Could not find %s node.\n", compat);
+ return;
+ }
+
+ ret = fdt_del_node(fdt, off);
+ if (ret < 0)
+ printf("Could not delete %s node.\n", compat);
+}
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+ flash_info_t *dev = &flash_info[0];
+ int off;
+ struct fdt_property *prop;
+ int len;
+ u32 *reg, *reg2;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+ if (off < 0) {
+ printf("Could not find fsl,mpc5200b-lpb node.\n");
+ return;
+ }
+
+ /* found compatible property */
+ prop = fdt_get_property_w(blob, off, "ranges", &len);
+ if (prop) {
+ reg = reg2 = (u32 *)&prop->data[0];
+
+ reg[2] = dev->start[0];
+ reg[3] = dev->size;
+ fdt_setprop(blob, off, "ranges", reg2, len);
+ } else
+ printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size (phys_addr_t base, int banknum);
+
+/* Update the Flash Baseaddr settings */
+int update_flash_size (int flash_size)
+{
+ volatile struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+ flash_info_t *dev;
+ int i;
+ int size = 0;
+ unsigned long base = 0x0;
+ u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+ for (i = 0; i < 2; i++) {
+ dev = &flash_info[i];
+
+ if (dev->size) {
+ /* calculate new base addr for this chipselect */
+ base -= dev->size;
+ out_be32(cs_reg, START_REG(base));
+ cs_reg++;
+ out_be32(cs_reg, STOP_REG(base, dev->size));
+ cs_reg++;
+ /* recalculate the sectoraddr in the cfi driver */
+ size += flash_get_size(base, i);
+ }
+ }
+ gd->bd->bi_flashstart = base;
+ return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+ /*
+ * There are 2 RTC nodes in the DTS, so remove
+ * the unneeded node here.
+ */
+#if defined(CONFIG_DIGSY_REV5)
+ ft_delete_node(blob, "dallas,ds1339");
+#else
+ ft_delete_node(blob, "mc,rv3029c2");
+#endif
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+ ft_adapt_flash_base(blob);
+#endif
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#endif /* CONFIG_CMD_IDE */
/*
- * (C) Copyright 2007
+ * (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
+ * based on:
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
-#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
-#define CONFIG_HOSTNAME mgsuvd
-
-#define CONFIG_SYS_TEXT_BASE 0xf0000000
-
-/* include common defines/options for all Keymile 8xx boards */
-#include "km8xx.h"
-
-#endif /* __CONFIG_H */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x50470000
+#define SDRAM_CONFIG1 0xD2322900
+#define SDRAM_CONFIG2 0x8AD70000
+++ /dev/null
-#
-# (C) Copyright 2007
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
- km8xx_hdlc_enet.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <mpc8xx.h>
-#include <net.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-#include "../common/common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const uint sdram_table[] =
-{
- 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
- 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- /* 0x08 Burst Read */
- 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
- 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
- /* 0x10 Load mode register */
- 0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- /* 0x18 Single Write */
- 0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
- 0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
- /* 0x20 Burst Write */
- 0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
- 0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
- 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- /* 0x30 Precharge all and Refresh */
- 0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
- 0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- /* 0x3C Exception */
- 0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
-};
-
-int checkboard (void)
-{
- puts ("Board: Keymile ");
-#if defined(CONFIG_KMSUPX4)
- puts ("kmsupx4");
-#else
- puts ("mgsuvd");
-#endif
- if (ethernet_present ())
- puts (" with PIGGY.");
- puts ("\n");
- return (0);
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
-
- upmconfig (UPMB, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /*
- * The following value is used as an address (i.e. opcode) for
- * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
- * the port size is 32bit the SDRAM does NOT "see" the lower two
- * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
- * MICRON SDRAMs:
- * -> 0 00 010 0 010
- * | | | | +- Burst Length = 4
- * | | | +----- Burst Type = Sequential
- * | | +------- CAS Latency = 2
- * | +----------- Operating Mode = Standard
- * +-------------- Write Burst Mode = Programmed Burst Length
- */
- memctl->memc_mar = CONFIG_SYS_MAR;
-
- /*
- * Map controller banks 1 to the SDRAM banks 1 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
- udelay (1);
- memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
- udelay (1);
-
- memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- */
- size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
-
- return (size);
-}
-
-/*
- * Early board initalization.
- */
-int board_early_init_r(void)
-{
- /* setup the UPIOx */
- /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
- out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
- /* SCC4 enable, halfduplex, FCC1 powerdown, ANDI enable*/
- out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x35);
- return 0;
-}
-
-int hush_init_var (void)
-{
- ivm_read_eeprom ();
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-/*
- * update "brg" property in the blob
- */
-void ft_blob_update (void *blob, bd_t *bd)
-{
- ulong brg_data[1] = {0};
-
- /* BRG */
- brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
- fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data,
- sizeof (brg_data));
-
- /* MAC adr */
- fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address",
- bd->bi_enetaddr, sizeof (u8) * 6);
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup (blob, bd);
- ft_blob_update (blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
-
-int i2c_soft_read_pin (void)
-{
- int val;
-
- *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF;
- udelay(1);
- val = *(unsigned char *)(I2C_BASE_PORT);
-
- return ((val & SDA_BIT) == SDA_BIT);
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
- *
- * Based in part on arch/powerpc/cpu/mpc8xx/scc.c.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h> /* commproc.h is included here */
-#include <malloc.h>
-#include <net.h>
-
-#ifdef CONFIG_KEYMILE_HDLC_ENET
-
-#include "../common/keymile_hdlc_enet.h"
-
-char keymile_slot; /* our slot number in the backplane */
-
-/*
- * Since, except during initialization, ethact is always HDLC
- * while we're in the driver, just use serial_printf() everywhere for
- * output. This avoids possible conflicts when netconsole is being
- * used.
- */
-#define dprintf(fmt, args...) serial_printf(fmt, ##args)
-
-static int already_inited;
-
-/*
- * SCC Ethernet Tx and Rx buffer descriptors allocated at the
- * immr->udata_bd address on Dual-Port RAM
- * Provide for Double Buffering
- */
-typedef volatile struct CommonBufferDescriptor {
- cbd_t txbd; /* Tx BD */
- cbd_t rxbd[HDLC_PKTBUFSRX]; /* Rx BD */
-} RTXBD;
-
-static RTXBD *rtx;
-
-int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
-void keymile_hdlc_enet_halt(struct eth_device *);
-extern void keymile_hdlc_enet_init_bds(RTXBD *);
-extern void initCachedNumbers(int);
-
-/* Use SCC4 */
-#define MGS_CPM_CR_HDLC CPM_CR_CH_SCC4
-#define MGS_PROFF_HDLC PROFF_SCC4
-#define MGS_SCC_HDLC 3 /* Index, not number! */
-
-int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis)
-{
- /* int i; */
- /* volatile cbd_t *bdp; */
- volatile cpm8xx_t *cp;
- volatile scc_t *sccp;
- volatile hdlc_pram_t *hpr;
- volatile iop8xx_t *iop;
-
- if (already_inited)
- return 0;
-
- cp = (cpm8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm);
- hpr = (hdlc_pram_t *)(&cp->cp_dparam[MGS_PROFF_HDLC]);
- sccp = (volatile scc_t *)(&cp->cp_scc[MGS_SCC_HDLC]);
- iop = (iop8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport);
-
- /*
- * Disable receive and transmit just in case.
- */
- sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
-#ifndef CONFIG_SYS_ALLOC_DPRAM
-#error "CONFIG_SYS_ALLOC_DPRAM must be defined"
-#else
- /*
- * Avoid exhausting DPRAM, which would cause a panic.
- * Actually this isn't really necessary, but leave it here
- * for safety's sake.
- */
- if (rtx == NULL) {
- rtx = (RTXBD *) (cp->cp_dpmem +
- dpram_alloc_align(sizeof(RTXBD), 8));
- if (rtx == (RTXBD *)CPM_DP_NOSPACE)
- return -1;
- memset((void *)rtx, 0, sizeof(RTXBD));
- }
-#endif /* !CONFIG_SYS_ALLOC_DPRAM */
-
- /* We need the slot number for addressing. */
- keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE +
- CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK;
- /*
- * Be consistent with the Linux driver and set
- * only enetaddr[0].
- *
- * Always add 1 to the slot number so that
- * there are no problems with an ethaddr which
- * is all 0s. This should be acceptable because
- * a board should never have a slot number of 255,
- * which is the broadcast address. The HDLC addressing
- * uses only the slot number.
- */
- dev->enetaddr[0] = keymile_slot + 1;
-
-#ifdef TEST_IT
- dprintf("slot %d\n", keymile_slot);
-#endif
-
- /* use pa8, pa9 pins for TXD4, RXD4 respectively */
- iop->iop_papar |= ((0x8000 >> 8) | (0x8000 >> 9));
- iop->iop_padir &= ~((0x8000 >> 8) | (0x8000 >> 9));
- iop->iop_paodr &= ~((0x8000 >> 8) | (0x8000 >> 9));
-
- /* also use pa0 as CLK8 */
- iop->iop_papar |= 0x8000;
- iop->iop_padir &= ~0x8000;
- iop->iop_paodr &= ~0x8000;
-
- /* use pc5 as CTS4 */
- iop->iop_pcpar &= ~(0x8000 >> 5);
- iop->iop_pcdir &= ~(0x8000 >> 5);
- iop->iop_pcso |= (0x8000 >> 5);
-
- /*
- * SI clock routing
- * use CLK8
- * this also connects SCC4 to NMSI
- */
- cp->cp_sicr = (cp->cp_sicr & ~0xff000000) | 0x3f000000;
-
- /* keymile_rxIdx = 0; */
-
- /*
- * Initialize function code registers for big-endian.
- */
- hpr->rfcr = SCC_EB;
- hpr->tfcr = SCC_EB;
-
- /*
- * Set maximum bytes per receive buffer.
- */
- hpr->mrblr = MAX_FRAME_LENGTH;
-
- /* Setup CRC generator values for HDLC */
- hpr->c_mask = 0x0000F0B8;
- hpr->c_pres = 0x0000FFFF;
-
- /* Initialize all error counters to 0 */
- hpr->disfc = 0;
- hpr->crcec = 0;
- hpr->abtsc = 0;
- hpr->nmarc = 0;
- hpr->retrc = 0;
-
- /* Set maximum frame length size */
- hpr->mflr = MAX_FRAME_LENGTH;
-
- /* set to 1 for per frame processing change later if needed */
- hpr->rfthr = 1;
-
- hpr->hmask = 0xff;
-
- hpr->haddr2 = SET_HDLC_UUA(keymile_slot);
- hpr->haddr3 = hpr->haddr2;
- hpr->haddr4 = hpr->haddr2;
- /* broadcast */
- hpr->haddr1 = HDLC_BCAST;
-
- hpr->rbase = (unsigned int) &rtx->rxbd[0];
- hpr->tbase = (unsigned int) &rtx->txbd;
-
-#if 0
- /*
- * Initialize the buffer descriptors.
- */
- bdp = &rtx->txbd;
- bdp->cbd_sc = 0;
- bdp->cbd_bufaddr = 0;
- bdp->cbd_sc = BD_SC_WRAP;
-
- /*
- * Setup RX packet buffers, aligned correctly.
- * Borrowed from net/net.c.
- */
- MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
- MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
- for (i = 1; i < HDLC_PKTBUFSRX; i++)
- MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
-
- bdp = &rtx->rxbd[0];
- for (i = 0; i < HDLC_PKTBUFSRX; i++) {
- bdp->cbd_sc = BD_SC_EMPTY;
- /* Leave space at the start for INET header. */
- bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
- INET_HDR_ALIGN);
- bdp++;
- }
- bdp--;
- bdp->cbd_sc |= BD_SC_WRAP;
-#else
- keymile_hdlc_enet_init_bds(rtx);
-#endif
-
- /* Let's re-initialize the channel now. We have to do it later
- * than the manual describes because we have just now finished
- * the BD initialization.
- */
- cp->cp_cpcr = mk_cr_cmd(MGS_CPM_CR_HDLC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
- while (cp->cp_cpcr & CPM_CR_FLG);
-
- sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC;
- /* CTSS=1 */
- sccp->scc_gsmrh = SCC_GSMRH_CTSS;
- /* NOF=0, RTE=1, DRT=0, BUS=1 */
- sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10));
-
-/* loopback for local testing */
-#ifdef GJTEST
- dprintf("LOOPBACK!\n");
- sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
-#endif
-
- /*
- * Disable all interrupts and clear all pending
- * events.
- */
- sccp->scc_sccm = 0;
- sccp->scc_scce = 0xffff;
-
- /*
- * And last, enable the transmit and receive processing.
- */
- sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
- dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name,
- MGS_SCC_HDLC + 1);
-
- /*
- * We may not get an ARP packet because ARP was already done on
- * a different interface, so initialize the cached values now.
- */
- initCachedNumbers(1);
-
- already_inited = 1;
-
- return 0;
-}
-
-void keymile_hdlc_enet_halt(struct eth_device *dev)
-{
-#if 0 /* just return, but keep this for reference */
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* maybe should do a graceful stop here? */
- immr->im_cpm.cp_scc[MGS_SCC_HDLC].scc_gsmrl &=
- ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-#endif
-}
-
-#endif /* CONFIG_KEYMILE_HDLC_ENET */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
*/
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
- printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
*/
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_FLASH_PASS_CS));
- printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
*/
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
- printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
*/
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
- printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
canmb powerpc mpc5xxx
cm5200 powerpc mpc5xxx
digsy_mtc powerpc mpc5xxx digsy_mtc
-digsy_mtc_LOWBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0xFF000000
digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000
+digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc - - digsy_mtc:DIGSY_REV5
+digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5
galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200
galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT
icecube_5200 powerpc mpc5xxx icecube - - IceCube
v37 powerpc mpc8xx
MHPC powerpc mpc8xx mhpc eltec
TOP860 powerpc mpc8xx top860 emk
-kmsupx4 powerpc mpc8xx km8xx keymile
-mgsuvd powerpc mpc8xx km8xx keymile
KUP4K powerpc mpc8xx kup4k kup
KUP4X powerpc mpc8xx kup4x kup
ELPT860 powerpc mpc8xx elpt860 LEOX
sh7763rdp sh sh4 sh7763rdp renesas -
sh7785lcr sh sh4 sh7785lcr renesas -
sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1
-MigoRsh sh4 MigoR renesas -
+MigoR sh sh4 MigoR renesas -
grsim_leon2 sparc leon2 - gaisler
gr_cpci_ax2000 sparc leon3 - gaisler
gr_ep2s60 sparc leon3 - gaisler
flash = &flash_info[id->num];
start_phys = flash->start[0] + part->offset;
- end_phys = start_phys + part->size;
+ end_phys = start_phys + part->size - 1;
for (i = 0; i < flash->sector_count; i++) {
if (flash->start[i] >= end_phys)
}
#endif
-#ifdef CONFIG_CMD_SHA1
+#ifdef CONFIG_CMD_SHA1SUM
int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long addr, len;
"compute SHA1 message digest",
"address count"
);
-#endif /* CONFIG_CMD_SHA1 */
+#endif /* CONFIG_CMD_SHA1SUM */
#ifdef CONFIG_CMD_UNZIP
U_BOOT_CMD(
--- /dev/null
+The common CFI driver provides this weak default implementation for
+flash_cmd_reset():
+
+void __flash_cmd_reset(flash_info_t *info)
+{
+ /*
+ * We do not yet know what kind of commandset to use, so we issue
+ * the reset command in both Intel and AMD variants, in the hope
+ * that AMD flash roms ignore the Intel command.
+ */
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
+void flash_cmd_reset(flash_info_t *info)
+ __attribute__((weak,alias("__flash_cmd_reset")));
+
+
+Some flash chips seems to have trouble with this reset sequence. In this case
+the board specific code can override this weak default version with a board
+specific function. For example the digsy_mtc board equipped with the M29W128GH
+from Numonyx needs this version to function properly:
+
+void flash_cmd_reset(flash_info_t *info)
+{
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+}
+
+see also:
+http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
.TP
.BI "\-A [" "architecture" "]"
-Set architecture. Pass -h as the architecture to see the list of supported architectures.
+Set architecture. Pass \-h as the architecture to see the list of supported architectures.
.TP
.BI "\-O [" "os" "]"
Set operating system. bootm command of u-boot changes boot method by os type.
-Pass -h as the OS to see the list of supported OS.
+Pass \-h as the OS to see the list of supported OS.
.TP
.BI "\-T [" "image type" "]"
Set image type.
-Pass -h as the image to see the list of supported image type.
+Pass \-h as the image to see the list of supported image type.
.TP
.BI "\-C [" "compression type" "]"
Set compression type.
-Pass -h as the compression to see the list of supported compression type.
+Pass \-h as the compression to see the list of supported compression type.
.TP
.BI "\-a [" "load addess" "]"
return;
}
- printf ("%s FLASH (%d x %d)",
+ printf ("%s flash (%d x %d)",
info->name,
(info->portwidth << 3), (info->chipwidth << 3));
if (info->size < 1024*1024)
size += flash_info[i].size;
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
#ifndef CONFIG_SYS_FLASH_QUIET_TEST
- printf ("## Unknown FLASH on Bank %d "
+ printf ("## Unknown flash on Bank %d "
"- Size = 0x%08lx = %ld MB\n",
i+1, flash_info[i].size,
flash_info[i].size >> 20);
u8 chip_id;
int r;
SMC_SELECT_BANK(dev, 3);
- chip_id = SMC_inw(dev, 0xA) & LAN91C96_REV_REVID;
+ chip_id = (SMC_inw(dev, 0xA) & LAN91C96_REV_CHIPID) >> 4;
SMC_SELECT_BANK(dev, 0);
for (r = 0; r < sizeof(supported_chips) / sizeof(struct id_type); r++)
if (chip_id == supported_chips[r].id)
COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o
COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
+COBJS-$(CONFIG_RTC_RV3029) += rv3029.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <rtc.h>
+
+#define RTC_RV3029_CTRL_RESET 0x04
+#define RTC_RV3029_CTRL_SYS_R (1 << 4)
+
+#define RTC_RV3029_CLOCK_PAGE 0x08
+#define RTC_RV3029_PAGE_LEN 7
+
+#define RV3029C2_W_SECONDS 0x00
+#define RV3029C2_W_MINUTES 0x01
+#define RV3029C2_W_HOURS 0x02
+#define RV3029C2_W_DATE 0x03
+#define RV3029C2_W_DAYS 0x04
+#define RV3029C2_W_MONTHS 0x05
+#define RV3029C2_W_YEARS 0x06
+
+#define RV3029C2_REG_HR_12_24 (1 << 6) /* 24h/12h mode */
+#define RV3029C2_REG_HR_PM (1 << 5) /* PM/AM bit in 12h mode */
+
+int rtc_get( struct rtc_time *tmp )
+{
+ int ret;
+ unsigned char buf[RTC_RV3029_PAGE_LEN];
+
+ ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CLOCK_PAGE, 1, buf, \
+ RTC_RV3029_PAGE_LEN);
+ if (ret) {
+ printf("%s: error reading RTC: %x\n", __func__, ret);
+ return -1;
+ }
+ tmp->tm_sec = bcd2bin( buf[RV3029C2_W_SECONDS] & 0x7f);
+ tmp->tm_min = bcd2bin( buf[RV3029C2_W_MINUTES] & 0x7f);
+ if (buf[RV3029C2_W_HOURS] & RV3029C2_REG_HR_12_24) {
+ /* 12h format */
+ tmp->tm_hour = bcd2bin(buf[RV3029C2_W_HOURS] & 0x1f);
+ if (buf[RV3029C2_W_HOURS] & RV3029C2_REG_HR_PM)
+ /* PM flag set */
+ tmp->tm_hour += 12;
+ } else
+ tmp->tm_hour = bcd2bin(buf[RV3029C2_W_HOURS] & 0x3f);
+
+ tmp->tm_mday = bcd2bin( buf[RV3029C2_W_DATE] & 0x3F );
+ tmp->tm_mon = bcd2bin( buf[RV3029C2_W_MONTHS] & 0x1F );
+ tmp->tm_wday = bcd2bin( buf[RV3029C2_W_DAYS] & 0x07 );
+ /* RTC supports only years > 1999 */
+ tmp->tm_year = bcd2bin( buf[RV3029C2_W_YEARS]) + 2000;
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+
+#ifdef RTC_DEBUG
+ printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
+
+#endif
+ return 0;
+}
+
+int rtc_set( struct rtc_time *tmp )
+{
+ int ret;
+ unsigned char buf[RTC_RV3029_PAGE_LEN];
+#ifdef RTC_DEBUG
+ printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+
+ if (tmp->tm_year < 2000) {
+ printf("RTC: year %d < 2000 not possible\n", tmp->tm_year);
+ return -1;
+ }
+ buf[RV3029C2_W_SECONDS] = bin2bcd(tmp->tm_sec);
+ buf[RV3029C2_W_MINUTES] = bin2bcd(tmp->tm_min);
+ buf[RV3029C2_W_HOURS] = bin2bcd(tmp->tm_hour);
+ /* set 24h format */
+ buf[RV3029C2_W_HOURS] &= ~RV3029C2_REG_HR_12_24;
+ buf[RV3029C2_W_DATE] = bin2bcd(tmp->tm_mday);
+ buf[RV3029C2_W_DAYS] = bin2bcd(tmp->tm_wday);
+ buf[RV3029C2_W_MONTHS] = bin2bcd(tmp->tm_mon);
+ tmp->tm_year -= 2000;
+ buf[RV3029C2_W_YEARS] = bin2bcd(tmp->tm_year);
+ ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CLOCK_PAGE, 1,
+ buf, RTC_RV3029_PAGE_LEN);
+
+ /* give the RTC some time to update */
+ udelay(1000);
+ return 0;
+}
+
+void rtc_reset (void)
+{
+ int ret;
+ unsigned char buf[RTC_RV3029_PAGE_LEN];
+
+ buf[0] = RTC_RV3029_CTRL_SYS_R;
+ ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_RESET, 1,
+ buf, 1);
+}
#include "gadget_chips.h"
-#define USB_NET_NAME "usb0"
+#define USB_NET_NAME "usb_ether"
#define atomic_read
extern struct platform_data brd;
/* unregister_netdev (dev->net);*/
/* free_netdev(dev->net);*/
+ dev->gadget = NULL;
set_gadget_data(gadget, NULL);
}
}
dev->net = &l_netdev;
- strcpy(dev->net->name, USB_NET_NAME);
dev->cdc = cdc;
dev->zlp = zlp;
goto fail;
}
+ /* Configure default mac-addresses for the USB ethernet device */
+#ifdef CONFIG_USBNET_DEV_ADDR
+ strlcpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));
+#endif
+#ifdef CONFIG_USBNET_HOST_ADDR
+ strlcpy(host_addr, CONFIG_USBNET_HOST_ADDR, sizeof(host_addr));
+#endif
+ /* Check if the user overruled the MAC addresses */
+ if (getenv("usbnet_devaddr"))
+ strlcpy(dev_addr, getenv("usbnet_devaddr"),
+ sizeof(dev_addr));
+
+ if (getenv("usbnet_hostaddr"))
+ strlcpy(host_addr, getenv("usbnet_hostaddr"),
+ sizeof(host_addr));
+
+ if (!is_eth_addr_valid(dev_addr)) {
+ error("Need valid 'usbnet_devaddr' to be set");
+ goto fail;
+ }
+ if (!is_eth_addr_valid(host_addr)) {
+ error("Need valid 'usbnet_hostaddr' to be set");
+ goto fail;
+ }
+
+ if (usb_gadget_register_driver(ð_driver) < 0)
+ goto fail;
+
dev->network_started = 0;
packet_received = 0;
return;
}
+ /* If the gadget not registered, simple return */
+ if (!dev->gadget)
+ return;
+
usb_gadget_disconnect(dev->gadget);
+ usb_gadget_unregister_driver(ð_driver);
}
static struct usb_gadget_driver eth_driver = {
int usb_eth_initialize(bd_t *bi)
{
- int status = 0;
struct eth_device *netdev = &l_netdev;
- sprintf(netdev->name, "usb_ether");
+ strlcpy(netdev->name, USB_NET_NAME, sizeof(netdev->name));
netdev->init = usb_eth_init;
netdev->send = usb_eth_send;
#ifdef CONFIG_MCAST_TFTP
#error not supported
#endif
- /* Configure default mac-addresses for the USB ethernet device */
-#ifdef CONFIG_USBNET_DEV_ADDR
- strncpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));
-#endif
-#ifdef CONFIG_USBNET_HOST_ADDR
- strncpy(host_addr, CONFIG_USBNET_HOST_ADDR, sizeof(host_addr));
-#endif
- /* Check if the user overruled the MAC addresses */
- if (getenv("usbnet_devaddr"))
- strncpy(dev_addr, getenv("usbnet_devaddr"),
- sizeof(dev_addr));
-
- if (getenv("usbnet_hostaddr"))
- strncpy(host_addr, getenv("usbnet_hostaddr"),
- sizeof(host_addr));
-
- /* Make sure both strings are terminated */
- dev_addr[sizeof(dev_addr)-1] = '\0';
- host_addr[sizeof(host_addr)-1] = '\0';
-
- if (!is_eth_addr_valid(dev_addr)) {
- error("Need valid 'usbnet_devaddr' to be set");
- status = -1;
- }
- if (!is_eth_addr_valid(host_addr)) {
- error("Need valid 'usbnet_hostaddr' to be set");
- status = -1;
- }
- if (status)
- goto fail;
-
- status = usb_gadget_register_driver(ð_driver);
- if (status < 0)
- goto fail;
-
eth_register(netdev);
return 0;
-
-fail:
- error("%s failed. error = %d", __func__, status);
- return status;
}
/*
* RTC configuration
*/
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_I2C_RTC_ADDR 0x56
+#define CONFIG_RTC_RV3029
+#else
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
+#endif
/*
* Flash configuration
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_FLASH_BASE 0xFE000000
+#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_CS1, \
+ CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+#else
#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#endif
+
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_CFG 0x0002DD00
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
+#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG 0x0002DD00
+#endif
+
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * configuration options, keymile 8xx board specific
- */
-
-#ifndef __CONFIG_KM8XX_H
-#define __CONFIG_KM8XX_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_KM8XX 1 /* on a km8xx board */
-
-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
-
-#if defined(CONFIG_KMSUPX4)
-#undef CONFIG_I2C_MUX /* no I2C mux on this board */
-#endif
-
-#define CONFIG_8xx_GCLK_FREQ 66000000
-
-#define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
-#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-
-#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation,
- * the default value is not
- * working
- */
-
-#define BOOTFLASH_START F0000000
-#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#define BOOTFLASH_START F0000000
-#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
-
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_ENV_IVM "EEprom_ivm=pca9544a:70:4 \0"
-#else
-#define CONFIG_ENV_IVM ""
-#endif
-
-#define MTDIDS_DEFAULT "nor0=app"
-#define MTDPARTS_DEFAULT \
- "mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free)," \
- "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var)," \
- "768k(cfg)"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "addcon=setenv bootargs ${bootargs} " \
- "console=ttyCPM0,${baudrate}\0" \
- "mtdids=nor0=app \0" \
- "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
- "partition=nor0,9 \0" \
- "new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0" \
- CONFIG_ENV_IVM \
- ""
-
-#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
-
-#define CONFIG_TIMESTAMP /* but print image timestmps */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xf0000000
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_SIZE 32
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#define CONFIG_ENV_BUFFER_PRINT 1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CONFIG_SYS_SYPCR 0xffffff89
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_SYS_SIUMCR 0x00610480
-#else
-#define CONFIG_SYS_SIUMCR 0x00610400
-#endif
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#if defined(CONFIG_MGSUVD)
-#define SCCR_MASK 0x01800000
-#else
-#define SCCR_MASK 0x00000000
-#endif
-#define CONFIG_SYS_SCCR 0x01800000
-
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing: Default value of OR0 after reset
- */
-#define CONFIG_SYS_OR0_PRELIM 0xfe000954
-#define CONFIG_SYS_BR0_PRELIM 0xf0000401
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR1_PRELIM 0xfc000800
-#define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
-
-#define CONFIG_SYS_MPTPR 0x0200
-/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
- 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_SYS_MBMR 0x10964111
-#else
-#define CONFIG_SYS_MBMR 0x20964111
-#endif
-#define CONFIG_SYS_MAR 0x00000088
-
-/*
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
-
-/* GPIO/PIGGY on CS3 initialization values
-*/
-#define CONFIG_SYS_PIGGY_BASE (0x30000000)
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
-#define CONFIG_SYS_BR3_PRELIM (0x30000401)
-#else
-#define CONFIG_SYS_OR3_PRELIM (0xf8000d26)
-#define CONFIG_SYS_BR3_PRELIM (0x30000401)
-#endif
-
-#define CONFIG_SCC3_ENET
-#define CONFIG_ETHPRIME "SCC"
-#define CONFIG_HAS_ETH0
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define I2C_SOFT_DECLARATIONS
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
-#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
-
-#define SDA_BIT 0x40
-#define SCL_BIT 0x80
-#define SDA_CONF 0x1000
-#define SCL_CONF 0x2000
-
-#define I2C_ACTIVE do {} while (0)
-#define I2C_TRISTATE do {} while (0)
-#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
-#define I2C_SDA(bit) if(bit) { \
- clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
- } else { \
- clrbits(8, I2C_BASE_PORT, SDA_BIT); \
- setbits(be16, I2C_BASE_DIR, SDA_CONF); \
- }
-#define I2C_SCL(bit) if(bit) { \
- clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
- } else { \
- clrbits(8, I2C_BASE_PORT, SCL_BIT); \
- setbits(be16, I2C_BASE_DIR, SCL_CONF); \
- }
-#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
-#else
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#endif
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
-#endif /* __CONFIG_KM8XX_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC852T 1 /* This is a MPC852T CPU */
-#define CONFIG_KMSUPX4 1 /* ...on a kmsupx4 board */
-#define CONFIG_HOSTNAME kmsupx4
-
-#define CONFIG_SYS_TEXT_BASE 0xf0000000
-
-/* include common defines/options for all Keymile 8xx boards */
-#include "km8xx.h"
-
-#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
- * running in RAM.
- */
-#endif /* __CONFIG_H */
--- /dev/null
+#ifndef _LINUX_CRC7_H
+#define _LINUX_CRC7_H
+#include <linux/types.h>
+
+extern const u8 crc7_syndrome_table[256];
+
+static inline u8 crc7_byte(u8 crc, u8 data)
+{
+ return crc7_syndrome_table[(crc << 1) ^ data];
+}
+
+extern u8 crc7(u8 crc, const u8 *buffer, size_t len);
+
+#endif
COBJS-$(CONFIG_BZIP2) += bzlib_randtable.o
COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o
COBJS-$(CONFIG_USB_TTY) += circbuf.o
+COBJS-y += crc7.o
COBJS-y += crc16.o
COBJS-y += crc32.o
COBJS-y += ctype.o
{
/* Round up to make sure size gives nice stack alignment */
DEFINE(GENERATED_GBL_DATA_SIZE,
- (sizeof(struct global_data)+15) & ~15);
+ (sizeof(struct global_data) + 15) & ~15);
DEFINE(GENERATED_BD_INFO_SIZE,
- (sizeof(struct bd_info)+15) & ~15);
+ (sizeof(struct bd_info) + 15) & ~15);
return 0;
}
--- /dev/null
+/*
+ * crc7.c
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/crc7.h>
+
+
+/* Table for CRC-7 (polynomial x^7 + x^3 + 1) */
+const u8 crc7_syndrome_table[256] = {
+ 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
+ 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
+ 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
+ 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
+ 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
+ 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
+ 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
+ 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
+ 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
+ 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
+ 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
+ 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
+ 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
+ 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
+ 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
+ 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
+ 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
+ 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
+ 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
+ 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
+ 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
+ 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
+ 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
+ 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
+ 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
+ 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
+ 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
+ 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
+ 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
+ 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
+ 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
+ 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
+};
+
+/**
+ * crc7 - update the CRC7 for the data buffer
+ * @crc: previous CRC7 value
+ * @buffer: data pointer
+ * @len: number of bytes in the buffer
+ * Context: any
+ *
+ * Returns the updated CRC7 value.
+ */
+u8 crc7(u8 crc, const u8 *buffer, size_t len)
+{
+ while (len--)
+ crc = crc7_byte(crc, *buffer++);
+ return crc;
+}
ln -s ${SRCTREE}/arch/${arch}/include/asm asm
LNPREFIX=${SRCTREE}/arch/${arch}/include/asm/
cd ../include
- rm -f asm
- ln -s ${SRCTREE}/arch/${arch}/include/asm asm
+ mkdir -p asm
else
cd ./include
rm -f asm
* Supported commands for configuration file
*/
static table_entry_t kwbimage_cmds[] = {
- {CMD_BOOT_FROM, "BOOT_FROM", "boot comand", },
+ {CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
{CMD_NAND_ECC_MODE, "NAND_ECC_MODE", "NAND mode", },
{CMD_NAND_PAGE_SIZE, "NAND_PAGE_SIZE", "NAND size", },
{CMD_SATA_PIO_MODE, "SATA_PIO_MODE", "SATA mode", },
projects / karo-tx-uboot.git / commitdiff