ARC: Trim arcregs.h

Move the various registers into appropriate headers

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 1b907c4656668cf5d68498a85111b78383263645..d72e13897172ac95b036b8b3b342dd90b897a8ab 100644 (file)
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -21,8 +21,10 @@
 #define ARC_REG_FP_BCR         0x6B    /* Single-Precision FPU */
 #define ARC_REG_DPFP_BCR       0x6C    /* Dbl Precision FPU */
 #define ARC_REG_MMU_BCR                0x6f
+#define ARC_REG_DC_BCR         0x72    /* Dcache */
 #define ARC_REG_DCCM_BCR       0x74    /* DCCM Present + SZ */
 #define ARC_REG_TIMERS_BCR     0x75
+#define ARC_REG_IC_BCR         0x77    /* Icache */
 #define ARC_REG_ICCM_BCR       0x78
 #define ARC_REG_XY_MEM_BCR     0x79
 #define ARC_REG_MAC_BCR                0x7a
@@ -95,78 +97,6 @@
 #define AUX_ITRIGGER           0x40d
 #define AUX_IPULSE             0x415
 
-/* Timer related Aux registers */
-#define ARC_REG_TIMER0_LIMIT   0x23    /* timer 0 limit */
-#define ARC_REG_TIMER0_CTRL    0x22    /* timer 0 control */
-#define ARC_REG_TIMER0_CNT     0x21    /* timer 0 count */
-#define ARC_REG_TIMER1_LIMIT   0x102   /* timer 1 limit */
-#define ARC_REG_TIMER1_CTRL    0x101   /* timer 1 control */
-#define ARC_REG_TIMER1_CNT     0x100   /* timer 1 count */
-
-#define TIMER_CTRL_IE          (1 << 0) /* Interupt when Count reachs limit */
-#define TIMER_CTRL_NH          (1 << 1) /* Count only when CPU NOT halted */
-
-/* MMU Management regs */
-#define ARC_REG_TLBPD0         0x405
-#define ARC_REG_TLBPD1         0x406
-#define ARC_REG_TLBINDEX       0x407
-#define ARC_REG_TLBCOMMAND     0x408
-#define ARC_REG_PID            0x409
-#define ARC_REG_SCRATCH_DATA0  0x418
-
-/* Bits in MMU PID register */
-#define MMU_ENABLE             (1 << 31)       /* Enable MMU for process */
-
-/* Error code if probe fails */
-#define TLB_LKUP_ERR           0x80000000
-
-/* TLB Commands */
-#define TLBWrite    0x1
-#define TLBRead     0x2
-#define TLBGetIndex 0x3
-#define TLBProbe    0x4
-
-#if (CONFIG_ARC_MMU_VER >= 2)
-#define TLBWriteNI  0x5                /* write JTLB without inv uTLBs */
-#define TLBIVUTLB   0x6                /* explicitly inv uTLBs */
-#else
-#undef TLBWriteNI              /* These cmds don't exist on older MMU */
-#undef TLBIVUTLB
-#endif
-
-/* Instruction cache related Auxiliary registers */
-#define ARC_REG_IC_BCR         0x77    /* Build Config reg */
-#define ARC_REG_IC_IVIC                0x10
-#define ARC_REG_IC_CTRL                0x11
-#define ARC_REG_IC_IVIL                0x19
-#if (CONFIG_ARC_MMU_VER > 2)
-#define ARC_REG_IC_PTAG                0x1E
-#endif
-
-/* Bit val in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE   0x1
-
-/* Data cache related Auxiliary registers */
-#define ARC_REG_DC_BCR         0x72
-#define ARC_REG_DC_IVDC                0x47
-#define ARC_REG_DC_CTRL                0x48
-#define ARC_REG_DC_IVDL                0x4A
-#define ARC_REG_DC_FLSH                0x4B
-#define ARC_REG_DC_FLDL                0x4C
-#if (CONFIG_ARC_MMU_VER > 2)
-#define ARC_REG_DC_PTAG                0x5C
-#endif
-
-/* Bit val in DC_CTRL */
-#define DC_CTRL_INV_MODE_FLUSH  0x40
-#define DC_CTRL_FLUSH_STATUS    0x100
-
-/* MMU Management regs */
-#define ARC_REG_PID            0x409
-#define ARC_REG_SCRATCH_DATA0  0x418
-
-/* Bits in MMU PID register */
-#define MMU_ENABLE             (1 << 31)       /* Enable MMU for process */
 
 /*
  * Floating Pt Registers
@@ -293,24 +223,6 @@ struct bcr_identity {
 #endif
 };
 
-struct bcr_mmu_1_2 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-       unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
-#else
-       unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
-#endif
-};
-
-struct bcr_mmu_3 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-       unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
-                    u_itlb:4, u_dtlb:4;
-#else
-       unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
-                    ways:4, ver:8;
-#endif
-};
-
 #define EXTN_SWAP_VALID     0x1
 #define EXTN_NORM_VALID     0x2
 #define EXTN_MINMAX_VALID   0x2
@@ -343,14 +255,6 @@ struct bcr_extn_xymem {
 #endif
 };
 
-struct bcr_cache {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-       unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
-#else
-       unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
-#endif
-};
-
 struct bcr_perip {
 #ifdef CONFIG_CPU_BIG_ENDIAN
        unsigned int start:8, pad2:8, sz:8, pad:8;

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index d5555fe4742a3f696c7c8ef72d6eae757b51469e..ad7cbcac0453464fc12b87107c43a4792b3a191b 100644 (file)
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -67,6 +67,41 @@
 extern void arc_cache_init(void);
 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
 extern void __init read_decode_cache_bcr(void);
+
+struct bcr_cache {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+       unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
+#else
+       unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
+#endif
+};
+
+#endif
+
+/* Instruction cache related Auxiliary registers */
+#define ARC_REG_IC_IVIC                0x10
+#define ARC_REG_IC_CTRL                0x11
+#define ARC_REG_IC_IVIL                0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_REG_IC_PTAG                0x1E
 #endif
 
+/* Bit val in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE   0x1
+
+/* Data cache related Auxiliary registers */
+#define ARC_REG_DC_IVDC                0x47
+#define ARC_REG_DC_CTRL                0x48
+#define ARC_REG_DC_IVDL                0x4A
+#define ARC_REG_DC_FLSH                0x4B
+#define ARC_REG_DC_FLDL                0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_REG_DC_PTAG                0x5C
+#endif
+
+/* Bit val in DC_CTRL */
+#define DC_CTRL_INV_MODE_FLUSH  0x40
+#define DC_CTRL_FLUSH_STATUS    0x100
+
+
 #endif /* _ASM_CACHE_H */

diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 56b02320f1a928b3614f7ec6de3604b2ff9f65b4..333df8eca6996f8dc23a9ea7bae6a8aea5337452 100644 (file)
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -18,6 +18,52 @@ typedef struct {
 #endif
 } mm_context_t;
 
+struct bcr_mmu_1_2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+       unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
+#else
+       unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
+#endif
+};
+
+struct bcr_mmu_3 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+       unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
+                    u_itlb:4, u_dtlb:4;
+#else
+       unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
+                    ways:4, ver:8;
+#endif
+};
+
+#endif
+
+/* MMU Management regs */
+#define ARC_REG_TLBPD0         0x405
+#define ARC_REG_TLBPD1         0x406
+#define ARC_REG_TLBINDEX       0x407
+#define ARC_REG_TLBCOMMAND     0x408
+#define ARC_REG_PID            0x409
+#define ARC_REG_SCRATCH_DATA0  0x418
+
+/* Bits in MMU PID register */
+#define MMU_ENABLE             (1 << 31)       /* Enable MMU for process */
+
+/* Error code if probe fails */
+#define TLB_LKUP_ERR           0x80000000
+
+/* TLB Commands */
+#define TLBWrite    0x1
+#define TLBRead     0x2
+#define TLBGetIndex 0x3
+#define TLBProbe    0x4
+
+#if (CONFIG_ARC_MMU_VER >= 2)
+#define TLBWriteNI  0x5                /* write JTLB without inv uTLBs */
+#define TLBIVUTLB   0x6                /* explicitly inv uTLBs */
+#else
+#undef TLBWriteNI              /* These cmds don't exist on older MMU */
+#undef TLBIVUTLB
 #endif
 
 #endif

diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 09f4309aa2c035332153cd5c6b9734fd2262d95b..32afa54a585d500613af51a6d97e9a7e70c775ff 100644 (file)
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -44,6 +44,17 @@
 #include <asm/clk.h>
 #include <asm/mach_desc.h>
 
+/* Timer related Aux registers */
+#define ARC_REG_TIMER0_LIMIT   0x23    /* timer 0 limit */
+#define ARC_REG_TIMER0_CTRL    0x22    /* timer 0 control */
+#define ARC_REG_TIMER0_CNT     0x21    /* timer 0 count */
+#define ARC_REG_TIMER1_LIMIT   0x102   /* timer 1 limit */
+#define ARC_REG_TIMER1_CTRL    0x101   /* timer 1 control */
+#define ARC_REG_TIMER1_CNT     0x100   /* timer 1 count */
+
+#define TIMER_CTRL_IE          (1 << 0) /* Interupt when Count reachs limit */
+#define TIMER_CTRL_NH          (1 << 1) /* Count only when CPU NOT halted */
+
 #define ARC_TIMER_MAX  0xFFFFFFFF
 
 /********** Clock Source Device *********/

diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 689ffd86d5e9d3dc786ac60e8bee1dab9ce7af8c..c0decc1f8d22386603fd743c3a965b1566873d88 100644 (file)
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -15,6 +15,7 @@
 #include <linux/uaccess.h>
 #include <linux/kdebug.h>
 #include <asm/pgalloc.h>
+#include <asm/mmu.h>
 
 static int handle_vmalloc_fault(struct mm_struct *mm, unsigned long address)
 {