+commit e881cb563e32f45832b7b6db77bdcd017adcbb41
+Author: Bruce Adler <bruce.adler@ccpu.com>
+Date: Fri Nov 2 13:15:42 2007 -0700
+
+ fix wording in README
+
+ Changed the wording to properly describe the shadowing
+ of the environment from ROM to RAM
+
+ Signed-off-by: Bruce Adler <bruce.adler@acm.org>
+
+commit ad845beef06245426c57b53dcdc01b7dc70e0d45
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Wed Oct 31 02:18:15 2007 +0900
+
+ blackfin: Move `-D__BLACKFIN__' to $(ARCH)_config.mk
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit ec22755799466c8a103664bb3a5e647bf9c238f4
+Author: Vlad Lungu <vlad@comsys.ro>
+Date: Thu Oct 25 16:08:14 2007 +0300
+
+ Trimmed some variables in ne2000.c
+
+ Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+
+commit eb6f214d3644b2a77968c176ed36dcf858cfe7e0
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Thu Oct 25 17:51:27 2007 +0800
+
+ Fix the issue of usb_kbd driver missing the scan code of key 'z'.
+
+ The scan code of the key 'z' is 0x1d, which should be handled.
+
+ The change has be tested on NOVATEK USB keyboard and ULI PCI OHCI
+ controller.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+
+commit bbf4796f6498fbade56d56eff3a0a49b299d93e5
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Thu Oct 25 17:30:04 2007 +0800
+
+ Fix USB support issue for MPC8641HPCN board.
+
+ The configuration file has already enabled USB, but it
+ missed definition of CFG_OHCI_SWAP_REG_ACCESS, the USB
+ on MPC8641HPCN can not work because of the wrong USB
+ register endian.
+
+ And add the USB command to U-Boot commands list.
+
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+
+commit 4e62041023dc3de9d98d977bb080235bc6d035e0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Wed Oct 24 18:16:01 2007 +0200
+
+ Use config_cmd_default.h instead of config_cmd_all.h
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 56622f87857439b1c221e9deef11a9d5bb5d4308
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Wed Oct 24 01:37:36 2007 +0200
+
+ TQM5200: Call usb_cpu_init() during board init
+
+ usb_cpu_init() configures GPS USB pins, clocks, etc. and
+ is required for proper operation of kernel USB subsystem.
+ This setup was previously done in the kernel by the fixup
+ code which is being removed, thus low level init must be
+ done by U-boot now.
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 29c29c0267fe857e72014ce90c5d35b2ef6302bd
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Tue Oct 23 16:25:50 2007 +0200
+
+ Fix typo in nfs.c
+
+ An obvious typo. Originally fixed in linkstation u-boot port.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 59543fe00a4ce720ef9f5aa7fb387c6daf1c7d78
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date: Tue Oct 23 14:35:05 2007 +0200
+
+ Fix a typo in cpu/mpc824x/interrupts.c
+
+ Since December 2003 the timer_interrupt_cpu() function in
+ cpu/mpc824x/interrupts.c contains what seems to be a superfluous
+ parameter. Remove it.
+
+ Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit c9e7b9b9a1700fe009678d1f9b41e6364ac5df2d
+Author: Sergej Stepanov <Sergej.Stepanov@ids.de>
+Date: Wed Oct 17 11:13:51 2007 +0200
+
+ add ft_cpu_setup(..) on mpc8260
+
+ Add ft_cpu_setup(..)-function to adapt it for use with libfdt
+ based on code from mpc5xxx
+
+ Sigend-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
+ --
+
+commit 6abd82e19ae93c0b4d104e50165e235915ec0875
+Author: Sergej Stepanov <Sergej.Stepanov@ids.de>
+Date: Wed Oct 17 11:18:42 2007 +0200
+
+ changes for IDS8247 board support
+
+ To get the IDS8247 board working following are done:
+ - FCC2 is deactivated
+ - FCC1 is activated
+ - I2C is activated
+ - CFI driver is activated
+ - Adapted for use with LIBFDT
+
+ Signed-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
+ --
+
+commit 8b6684a698500be9c142ec2c9f46cfc348e17f0c
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed Oct 24 15:48:37 2007 +0200
+
+ ATSTK1002: Remove default ethernet addresses
+
+ Wolfgang is right: It's not a good idea to set up default initial
+ ethernet addresses for a board, even though they belong to the local
+ range.
+
+ This will change the failure mode from "IT manager screams at you for
+ using duplicate ethernet addresses" to a nice error message explaining
+ that the ethernet address hasn't been set properly.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit e5c794e491a57d829b6d8733e2ed8368a2269abf
+Author: Justin Flammia <jflammia@savantav.com>
+Date: Mon Oct 29 17:40:35 2007 -0400
+
+ DHCP Client Fix
+
+ This is a multi-part message in MIME format.
+
+ commit e6e505eae94ed721e123e177489291fc4544b7b8
+ Author: Justin Flammia <jflammia@savantav.com>
+ Date: Mon Oct 29 17:19:03 2007 -0400
+
+ Found a bug in the way the DHCP Request packet is built, where the IP address
+ that is offered by the server is bound to prematurely. This patch is a fix of
+ that bug where the IP address offered by the DHCP server is not used until
+ after the DHCP ACK from the server is received.
+
+ Signed-off-by: Justin Flammia <jflammia@savantav.com>
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+commit e8ee8f3ade2a06c1893dd5e68f223070d650c7ed
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:16:22 2007 -0500
+
+ ColdFire 54455: Fix correct boot location for atmel and intel
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 688e8eb414ac111cca7ce60bdf30e805ab9a7bcb
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:14:00 2007 -0500
+
+ ColdFire: Fix build error when CONFIG_WATCHDOG is defined
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit c67e12e705b204cfe914e3e3e693d69a445dcabf
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:12:36 2007 -0500
+
+ ColdFire 5329: Assign correct SDRAM size and fix cache
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 95e9f2c212a65610b2e59a5c00d0113383a4da0b
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:10:23 2007 -0500
+
+ ColdFire 5253: Assign correct SDRAM size
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit 2acefa72ee0026f862ab65597ca687428f63a973
+Author: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+Date: Thu Oct 25 17:09:17 2007 -0500
+
+ ColdFire 5282: Fix external flash boot and return dramsize
+
+ Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
+
+commit d78791ae914d4e7c5edca1cdad73b3dc81a4eb82
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Thu Oct 25 17:20:01 2007 +0200
+
+ TQM5200: increase kernel_addr_r and fdt_addr_r (hinted by Wolfgang Denk).
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 1a0ce20aa4cb4e3068da04e7290ee9986fd0b834
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Wed Oct 24 08:42:25 2007 +0200
+
+ TQM5200: fix spurious characters on second serial interface
+
+ With this patch PSC3 is configured as UART. This is done, because if
+ the pins of PSC3 are not configured at all (-> all pins are GPI),
+ due to crosstalk, spurious characters may be send over the RX232_2_TXD
+ signal line.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit be4a87f11e297a5cededbf7dd71c0248f3874acd
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Wed Oct 24 08:41:27 2007 +0200
+
+ TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller
+
+ Some commands for the STK52xx base board try to access the SM501 grafic
+ controller. But the TQM5200S has no grafic controller (only the TQM5200
+ and the TQM5200B have). This patch deactivates the commands accessing
+ the SM501 for the TQM5200S.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit b31f64343ead9482cd439b1adbe4c34026a641b1
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Oct 22 16:45:53 2007 +0200
+
+ TQM5200: fix spurious characters on second serial interface
+
+ With this patch PSC3 is configured as UART. This is done, because if
+ the pins of PSC3 are not configured at all (-> all pins are GPI),
+ due to crosstalk, spurious characters may be send over the RX232_2_TXD
+ signal line.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 0fc0f91b20ffa802f5a66534ca5c2844910583f6
+Author: Martin Krause <martin.krause@tqs.de>
+Date: Mon Oct 22 16:40:06 2007 +0200
+
+ TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller
+
+ Some commands for the STK52xx base board try to access the SM501 grafic
+ controller. But the TQM5200S has no grafic controller (only the TQM5200
+ and the TQM5200B have). This patch deactivates the commands accessing
+ the SM501 for the TQM5200S.
+
+ Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 7b0a42219f30277f71f4405cbaf8a269f6d2d227
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Oct 21 09:14:28 2007 +0200
+
+ Mips: Fix string functions differ prototype declaration
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Fri Oct 19 17:51:40 2007 -0500
+
+ fsl_pci_init enable COMMAND_MEMORY if inbound window
+
+ Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows
+ to pciauto_setup_device has the side effect of not getting
+ COMMAND_MEMORY set.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit e9d0d527992566ebef9826962ff1745b2f082b92
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 10:55:24 2007 +0200
+
+ delta: Fix OHCI_REGS_BASE undeclared and wait_ms implicit declaration
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9c4884f54da982ce990c7d1760ac81b0704d3c64
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 08:10:15 2007 +0200
+
+ fix warning: no return statement in function returning non-void
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e78220f6e514206757acfe247297fc9a328a881f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 06:33:45 2007 +0200
+
+ xsengine: Fix no partition type specified, use DOS as default
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 10cdb8dbd67a818823ab9ec88b68fc348903db59
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Fri Oct 19 00:24:59 2007 +0200
+
+ lubbock: Fix no partition type specified, use DOS as default
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 41b4d282d38fa7231c315c5f6cfff5bdd24e0191
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Oct 23 16:50:03 2007 +0200
+
+ Coding style: keep lists sorted; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 58b74b05c621e2835ecf4e2d3243042cf4186777
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri Oct 19 00:09:05 2007 +0200
are added to u-boot.
Signed-off-by Rune Torgersen <runet@innovsys.com>
+commit d3afa1ee19345a31fd1eaad3e98b97d13ca47315
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Tue Oct 23 13:14:10 2007 +0200
+
+ Motion-PRO: Update configuration to accomodate next generation board.
+
+ New board has faster oscillator and a different Flash chip. This affects:
+ - CFG_MPC5XXX_CLKIN
+ - SDRAM timings
+ - Flash CS configuration (timings)
+ - Flash sector size, and thus MTD partition layout
+ - malloc() arena size (due to bigger Flash sectors)
+ - smaller memory test range (due to bigger malloc() arena)
+
+ This patch also enables more extensive memory testing via "mtest".
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit eff501904df2bf1724a750062628ba2c51dbb1f8
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Tue Oct 23 11:36:07 2007 +0200
+
+ Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration.
+
+ Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
+ register must be written a value of 0x00000004 as the first step of the
+ SDRAM contorller configuration.
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 7a9348728ebda63cdbaacffd83099aa71d9d4c54
+Author: Peter Pearse <peter.pearse@arm.com>
+Date: Tue Oct 23 10:22:16 2007 +0100
+
+ Move PL01* serial drivers to drivers/serial and adjust Makefiles.
+
+commit de9a738faa7c2f47286119c3bfebc3dfbfe7d86d
+Author: Vlad Lungu <vlad@comsys.ro>
+Date: Sun Oct 21 22:10:10 2007 +0900
+
+ [MIPS] Fix UNCACHED_SDRAM
+
+ PHYSADDR is for physical address, KSEG1ADDR is for uncached.
+
+ Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 00101dd7a32d12f698150123e47e4b3420279f86
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 21:30:42 2007 +0900
+
+ [MIPS] Add PIC-related switches to PLATFORM_{CPP,LD}FLAGS and cleanup
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit eb700636db017d310edaeb559b13d82588560674
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:37 2007 +0900
+
+ [MIPS] u-boot.lds: Define _gp in a standard manner
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit 22069215eb7adf5a3888bf7c7784ea9d70a72cd0
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:36 2007 +0900
+
+ [MIPS] Fix $gp usage
+
+ Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use.
+ As a general principle, we should use _gp for $gp.
+
+ Thanks to linker script's help we fortunately have _gp which equals to
+ _GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not
+ be able to access to GOT entires, global variables and procedure entry
+ points. The right thing to do is to use _gp.
+
+ This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_'
+ which holds the offset from _gp. When updating GOT entries, we use this
+ offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_.
+
+ This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then
+ I made some change to leave over num_got_entries.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+ Cc: Vlad Lungu <vlad@comsys.ro>
+
+commit cbf2323b5b8285ea01acba7bbb905a3162d9b021
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:36 2007 +0900
+
+ [MIPS] u-boot.lds: Fix __got_start and __got_end
+
+ Ensure that __got_start points to top of the `.got', and __got_end points
+ to bottom as well, so that we never fail to count num_got_entries.
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit e5f325fec5b48ae705c89522923ba5a2e37cd5c7
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Sun Oct 21 10:55:36 2007 +0900
+
+ [MIPS] u-boot.lds: Remove duplicated .sdata section
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
commit 05bf4919c1ce49cdedadacd564d0786a8ed796a1
Author: Wolfgang Denk <wd@denx.de>
Date: Sun Oct 21 01:01:17 2007 +0200
Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+commit df90968b48fb34fa9072fab150db2ac89678f537
+Author: urwithsughosh@gmail.com <urwithsughosh@gmail.com>
+Date: Mon Sep 24 13:32:13 2007 -0400
+
+ Setting MSR[DE] in do_reset
+
+ Hello,
+ This patch ensures the soft reset of the board for the 85xx boards
+ by setting the MSR[DE] in the do_reset function.
+
+ Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
+
+commit 1e701e701304b3c3a3768ca83dd2ab7b9e88c77d
+Author: urwithsughosh@gmail.com <urwithsughosh@gmail.com>
+Date: Mon Sep 24 13:36:01 2007 -0400
+
+ MSR overwrite fix
+
+ Hello,
+ This patch fixes the MSR overwrite in the start.S when moving out of
+ the last 4K page.
+
+ Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
+
+commit 5c7ea64bb74a850a2b2303f853a8270695ad8602
+Author: Dan Wilson <dwilson@fulcrummicro.com>
+Date: Fri Oct 19 11:33:48 2007 -0500
+
+ tsec driver should clear RHALT on startup
+
+ This was causing problems for some people.
+
+ Signed-off-by: Alain Gravel <agravel@fulcrummicro.com>
+ Signed-off-by: Dan Wilson <dwilson@fulcrummicro.com>
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 7600d47b8f6a10019e537dc9a62aa1498df58d25
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Oct 11 00:29:18 2007 -0500
+
+ Improve handling of PCI interrupt device tree fixup on MPC85xx CDS
+
+ On the MPC85xx CDS we have two issues:
+
+ 1. The device tree fixup code did not check to see if the property we are
+ trying to update is actually found. Its possible that it would update
+ random memory starting at 0.
+
+ 2. Newer Linux kernel's have moved the location of the PCI nodes to be
+ sibilings of the soc node and not children. The explicit PATH to the PCI
+ node would not be found for these device trees. Add the ability to handle
+ both paths. In the future we shouldn't handle such fixups by explicit path.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a3063eec775719b7e91023bbec3f64b3118791df
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Oct 11 00:18:48 2007 -0500
+
+ Set OF_STDOUT_PATH to match the default console on MPC8568 MDS
+
+ On the MPC8568 MDS we use ttyS0, UART0, etc. as the standard configured
+ console. Make it so we match that config what we tell Linux as the early
+ STDOUT console.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e1ce3cb617bb06f91f82f98915391175addf3e82
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Oct 2 11:12:27 2007 -0500
+
+ Remove magic numbers from cache related operations for mpc85xx
+
+ The mpc85xx start code uses some magic numbers that we actually
+ have #defines for in <config.h> so use those instead.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
commit 5441f61a3d8b7034f19fc1361183e936198e6dbb
Author: Detlev Zundel <dzu@denx.de>
Date: Fri Oct 19 16:47:26 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
+commit 1487adbdcf9594bb2eb686325a6f9540dad1b70a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date: Wed Sep 26 16:35:54 2007 -0500
+
+ 85xx io out functions need sync after write.
+
+ This fixes the mc146818 rtc_read/write functions for 85xx.
+
+ Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
commit 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Tue Sep 25 15:48:05 2007 -0600
>include/config.h ; \
if [ "$${FLASH}" == "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+ echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+ cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with INTEL boot..." ; \
else \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+ echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+ cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
echo "... with ATMEL boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
to be a good choice since it makes it far enough from the
start of the data area as well as from the stack pointer.
-Please note that the environment is read-only as long as the monitor
+Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_r()
until then to read environment variables.
# MA 02111-1307 USA
#
-PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__BLACKFIN__
map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
- len /= sizeof(u32);
+ if (!map)
+ map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
- slot = get_pci_slot();
+ if (map) {
+ len /= sizeof(u32);
- for (i=0;i<len;i+=7) {
- /* We rotate the interrupt pins so that the mapping
- * changes depending on the slot the carrier card is in.
- */
- map[3] = ((map[3] + slot - 2) % 4) + 1;
+ slot = get_pci_slot();
- map+=7;
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+
+ map+=7;
+ }
+ } else {
+ printf("*** Warning - No PCI node found\n");
}
}
#endif
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- _gp = ALIGN(16);
-
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
#include <ioports.h>
#include <mpc8260.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/*
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */
- /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
- /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
- /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
- /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
- /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
+ /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
+ /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
+ /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
+ /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
+ /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
+ /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
#if defined(CONFIG_SOFT_I2C)
/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
#endif
/* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
+ /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
+ /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
+ /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
+ /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
+ /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
+ /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
+ /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
+ /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
/* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
/* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
/* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
+ /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */
+ /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
- maxsize = (1 + (~orx | 0x7fff)) / 2;
+ maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
sdmr_ptr = &memctl->memc_psdmr;
orx_ptr = &memctl->memc_or2;
printf ("%4lu MB\n", totlen >>20);
}
-#endif
+#endif /* CFG_CMD_NAND */
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * update "memory" property in the blob
+ */
+void ft_blob_update(void *blob, bd_t *bd)
+{
+ int ret, nodeoffset = 0;
+ ulong memory_data[2] = {0};
+
+ memory_data[0] = cpu_to_be32(bd->bi_memstart);
+ memory_data[1] = cpu_to_be32(bd->bi_memsize);
+
+ nodeoffset = fdt_find_node_by_path (blob, "/memory");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
+ sizeof(memory_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /memory/reg "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /memory node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup( blob, bd);
+ ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
/* Write to the SDRAM Mode Register */
*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
}
+ return dramsize;
}
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- _gp = ALIGN(16);
-
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
-
- _gp = ALIGN(16);
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
}
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
-#ifdef CONFIG_PS2MULT
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
+#ifdef CONFIG_PS2MULT
ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+ /* Low level USB init, required for proper kernel operation */
+ usb_cpu_init();
+#endif
+
return (0);
}
#endif
-#endif /* CONFIG_PS2MULT */
#ifdef CONFIG_FO300
int silent_boot (void)
repeat_delay=REPEAT_DELAY;
}
keycode=0;
- if((scancode>3) && (scancode<0x1d)) { /* alpha numeric values */
+ if((scancode>3) && (scancode<=0x1d)) { /* alpha numeric values */
keycode=scancode-4 + 0x61;
if(caps_lock)
keycode&=~CAPITAL_MASK; /* switch to capital Letters */
endif
endif
-ifeq ($(ARCH),blackfin)
-PLATFORM_CPPFLAGS+= -D__BLACKFIN__
-endif
-
ifdef ARCH
sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
endif
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_R5200)
.long 0x400
-#elif defined(CONFIG_M5282)
+#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+ move.l #CFG_INT_FLASH_BASE, %d0
+#else
move.l #CFG_FLASH_BASE, %d0
+#endif
movec %d0, %VBR
#endif
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
- move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0
+ move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */
ENDIANNESS = -EB
endif
-MIPSFLAGS += $(ENDIANNESS) -mabicalls
+MIPSFLAGS += $(ENDIANNESS)
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
- /* Initialize GOT pointer.
+ /* Initialize $gp.
*/
bal 1f
nop
- .word _GLOBAL_OFFSET_TABLE_
+ .word _gp
1:
move gp, ra
lw t1, 0(ra)
move t1, a2
/*
- * Fix GOT pointer:
+ * Fix $gp:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
j t0
nop
+ .gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
- /* Now we want to update GOT.
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
- addi t4, gp, 8 /* Skipping first two entries. */
+ lw t4, -16(t0) /* t4 <-- (_GLOBAL_OFFSET_TABLE_ - _gp) */
+ add t4, t4, gp /* t4 now holds _GLOBAL_OFFSET_TABLE_ */
+ addi t4, t4, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)
vga?
*/
-void timer_interrupt_cpu (struct pt_regs *regs, ulong timestamp)
+void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
#include <asm/processor.h>
#include <asm/cpm_8260.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_GET_CPU_STR_F)
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_OF_LIBFDT)
+static void do_fixup(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create)
+{
+#if defined(DEBUG)
+ int i;
+ debug("Updating property '%s/%s' = ", node, prop);
+ for (i = 0; i < len; i++)
+ debug(" %.2x", *(u8*)(val+i));
+ debug("\n");
+#endif
+ int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create);
+ if (rc)
+ printf("Unable to update property %s:%s, err=%s\n",
+ node, prop, fdt_strerror(rc));
+}
+
+static void do_fixup_u32(void *fdt, const char *node, const char *prop,
+ u32 val, int create)
+{
+ val = cpu_to_fdt32(val);
+ do_fixup(fdt, node, prop, &val, sizeof(val), create);
+}
+
+void ft_cpu_setup (void *blob, bd_t *bd)
+{
+ char * cpu_path = "/cpus/" OF_CPU;
+
+ do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
+ do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
+}
+#endif /* CONFIG_OF_LIBFDT */
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
- unsigned long val;
+ unsigned long val, msr;
+
+ msr = mfmsr ();
+ msr |= MSR_DE;
+ mtmsr (msr);
+
val = mfspr(DBCR0);
val |= 0x70000000;
mtspr(DBCR0,val);
bdnz 0b
/* Clear and set up some registers. */
+ li r0,0
+ mtmsr r0
li r0,0x0000
lis r1,0xffff
mtspr DEC,r0 /* prevent dec exceptions */
*/
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
- li r2,512 /* 512*32=16K */
+ li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r2
li r0,0
1:
dcbz r0,r3
dcbtls 0,r0,r3
- addi r3,r3,32
+ addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
#ifdef CFG_RAMBOOT
- bl 3f
b _start_cont
#else
/* Calculate absolute address in FLASH and jump there */
ori r3,r3,CFG_MONITOR_BASE@l
addi r3,r3,_start_cont - _start + _START_OFFSET
mtlr r3
+ blr
#endif
-3: li r0,0
- mtspr SRR1,r0 /* Keep things disabled for now */
- mflr r1
- mtspr SRR0,r1
- rfi
- isync
-
.text
.globl _start
_start:
.globl out8
out8:
stb r4,0x0000(r3)
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out16
out16:
sth r4,0x0000(r3)
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out16r
out16r:
sthbrx r4,r0,r3
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out32
out32:
stw r4,0x0000(r3)
+ sync
blr
/*------------------------------------------------------------------------------- */
.globl out32r
out32r:
stwbrx r4,r0,r3
+ sync
blr
/*------------------------------------------------------------------------------- */
/* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
- li r4,512
+ li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r4
1: icbi r0,r3
dcbi r0,r3
- addi r3,r3,32
+ addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync
s3c4510b_eth.o s3c4510b_uart.o \
sed13806.o sed156x.o \
serial.o serial_max3100.o \
- serial_pl010.o serial_pl011.o serial_xuartlite.o \
+ serial_xuartlite.o \
sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
status_led.o sym53c8xx.o systemace.o ahci.o \
ti_pci1410a.o tigon3.o tqm8xx_pcmcia.o tsec.o \
{ /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 },
{ /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
{ /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 },
- { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 }
+ { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 },
+ { /* Qemu */ 0x0, 0x52, 0x54, 0x00, 0 }
};
#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t))
/* U-boot specific routines */
-#define NB 5
static unsigned char *pbuf = NULL;
-static int plen[NB];
-static int nrx = 0;
static int pkey = -1;
static int initialized=0;
void uboot_push_packet_len(int len) {
- PRINTK("pushed len = %d, nrx = %d\n", len, nrx);
+ PRINTK("pushed len = %d\n", len);
if (len>=2000) {
printf("NE2000: packet too big\n");
return;
}
- if (nrx >= NB) {
- printf("losing packets in rx\n");
- return;
- }
- plen[nrx] = len;
- dp83902a_recv(&pbuf[nrx*2000], len);
+ dp83902a_recv(&pbuf[0], len);
/*Just pass it to the upper layer*/
- NetReceive(&pbuf[nrx*2000], plen[nrx]);
+ NetReceive(&pbuf[0], len);
}
void uboot_push_tx_done(int key, int val) {
PRINTK("### eth_init\n");
if (!pbuf) {
- pbuf = malloc(NB*2000);
+ pbuf = malloc(2000);
if (!pbuf) {
- printf("Cannot allocate rx buffers\n");
+ printf("Cannot allocate rx buffer\n");
return -1;
}
}
LIB := $(obj)libserial.a
-COBJS := mcfuart.o
+COBJS := mcfuart.o serial_pl010.o serial_pl011.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/* Tell the DMA it is clear to go */
regs->dmactrl |= DMACTRL_INIT_SETTINGS;
regs->tstat = TSTAT_CLEAR_THALT;
+ regs->rstat = RSTAT_CLEAR_RHALT;
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
}
. = ALIGN(4);
.data : { *(.data) }
- . = ALIGN(4);
- .sdata : { *(.sdata) }
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
- _gp = ALIGN(16);
-
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
.sdata : { *(.sdata) }
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_AU1X00 */
-#define UNCACHED_SDRAM(a) PHYSADDR(a)
+#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
#endif /* CONFIG_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_NAND
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_VFD
-#undef CONFIG_CMD_USB
#undef CONFIG_CMD_XIMG
-#if (CFG_NIOS_CPU_SPI_NUMS != 1)
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_DATE
+#if (CFG_NIOS_CPU_SPI_NUMS == 1)
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_SPI
#endif
/*------------------------------------------------------------------------
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_DATE
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_NAND
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_VFD
-#undef CONFIG_CMD_USB
#undef CONFIG_CMD_XIMG
-
/*------------------------------------------------------------------------
* COMPACT FLASH
*----------------------------------------------------------------------*/
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef COND_CMD_BEDBUG
-#undef COND_CMD_BMP
-#undef COND_CMD_BSP
-#undef COND_CMD_CACHE
-#undef COND_CMD_DATE
-#undef COND_CMD_DOC
-#undef COND_CMD_DTT
-#undef COND_CMD_EEPROM
-#undef COND_CMD_ELF
-#undef COND_CMD_FAT
-#undef COND_CMD_FDC
-#undef COND_CMD_FDOS
-#undef COND_CMD_HWFLOW
-#undef COND_CMD_IDE
-#undef COND_CMD_I2C
-#undef COND_CMD_JFFS2
-#undef COND_CMD_KGDB
-#undef COND_CMD_NAND
-#undef COND_CMD_NFS
-#undef COND_CMD_MMC
-#undef COND_CMD_MII
-#undef COND_CMD_PCI
-#undef COND_CMD_PCMCIA
-#undef COND_CMD_SCSI
-#undef COND_CMD_SPI
-#undef COND_CMD_VFD
-#undef COND_CMD_USB
-#undef COND_CMD_XIMG
-
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
/*------------------------------------------------------------------------
* KGDB
#define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8247@0"
+#define OF_SOC "soc@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
+
+
/*
* select ethernet configuration
*
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
+#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
+#define CONFIG_ETHER_ON_FCC1
+#define FCC_ENET
/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
+ * - Rx-CLK is CLK10
+ * - Tx-CLK is CLK9
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
* - Enable Full Duplex in FSMR
*/
-# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
# define CFG_CPMFCR_RAMTYPE 0
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR 0x51
/*
* Command line configuration.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_BANKS_LIST { 0xFF800000 }
+#define CFG_MAX_FLASH_BANKS_DETECT 1
/* What should the base address of the main FLASH be and how big is
* it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
* The main FLASH is whichever is connected to *CS0.
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
*/
#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A10 |\
+ ORxS_ROWST_PBI0_A9 |\
ORxS_NUMR_12)
-#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\
+#define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
PSDMR_BSMA_A15_A17 |\
- PSDMR_SDA10_PBI0_A11 |\
+ PSDMR_SDA10_PBI0_A10 |\
PSDMR_RFRC_5_CLK |\
PSDMR_PRETOACT_2W |\
PSDMR_ACTTORW_2W |\
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_XIMG
#if !(CONFIG_LANTEC >= 2)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000
#define CFG_INT_FLASH_ENABLE 0x21
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x40000000
-#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x53722730
#define CFG_SDRAM_CFG2 0x56670000
#define CFG_SDRAM_CTRL 0xE1092000
* board/config.h - configuration options, board specific
*/
-#ifndef _JAMICA54455_H
-#define _JAMICA54455_H
+#ifndef _M54455EVB_H
+#define _M54455EVB_H
/*
* High Level Configuration Options
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 2ffff;" \
- "era 0 2ffff;" \
+ "prog=prot off 4000000 402ffff;" \
+ "era 4000000 402ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CFG_IMMR CFG_MBAR
/* PCI */
+#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CFG_PCI_MEM_BUS 0xA0000000
#define CFG_PCI_CFG_BUS 0xB0000000
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
#define CFG_PCI_CFG_SIZE 0x01000000
+#endif
/* FPGA - Spartan 2 */
/* experiment
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
-#define CFG_ENV_OFFSET 0x4000
-#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OVERWRITE 1
#undef CFG_ENV_IS_EMBEDDED
* FLASH organization
*/
#ifdef CFG_ATMEL_BOOT
-# define CFG_FLASH_BASE 0
+# define CFG_FLASH_BASE CFG_CS0_BASE
# define CFG_FLASH0_BASE CFG_CS0_BASE
# define CFG_FLASH1_BASE CFG_CS1_BASE
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
+# define CFG_ENV_SECT_SIZE 0x2000
#else
# define CFG_FLASH_BASE CFG_FLASH0_BASE
# define CFG_FLASH0_BASE CFG_CS1_BASE
# define CFG_FLASH1_BASE CFG_CS0_BASE
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
+# define CFG_ENV_SECT_SIZE 0x20000
#endif
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#ifdef CFG_ATMEL_BOOT
-# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_DEV "nor1"
# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
+# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000)
#else
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
#ifdef CFG_ATMEL_BOOT
/* Atmel Flash */
-#define CFG_CS0_BASE 0
+#define CFG_CS0_BASE 0x04000000
#define CFG_CS0_MASK 0x00070001
#define CFG_CS0_CTRL 0x00001140
/* Intel Flash */
-#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_BASE 0x00000000
#define CFG_CS1_MASK 0x01FF0001
-#define CFG_CS1_CTRL 0x003F3D60
+#define CFG_CS1_CTRL 0x00000D60
#define CFG_ATMEL_BASE CFG_CS0_BASE
#else
/* Intel Flash */
-#define CFG_CS0_BASE 0
+#define CFG_CS0_BASE 0x00000000
#define CFG_CS0_MASK 0x01FF0001
-#define CFG_CS0_CTRL 0x003F3D60
+#define CFG_CS0_CTRL 0x00000D60
/* Atmel Flash */
#define CFG_CS1_BASE 0x04000000
#define CFG_CS1_MASK 0x00070001
#define CFG_CS3_MASK 0x00070001
#define CFG_CS3_CTRL 0x00000020
-#endif /* _JAMICA54455_H */
+#endif /* _M54455EVB_H */
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_DATE
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_SNTP
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+
#undef CONFIG_CMD_XIMG
#if CONFIG_ADSTYPE == CFG_8272ADS
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
+#define OF_PCI "pci@e0008000"
/*
* I2C
#define OF_SOC "soc8568@e0000000"
#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
+#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
/*
* I2C
#define CFG_USB_EVENT_POLL 1
#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_OHCI_SWAP_REG_ACCESS 1
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_USB
#endif
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BSP
-#undef CONFIG_CMD_DATE
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+
#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SNTP
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
#undef CONFIG_CMD_XIMG
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
- * These are "locally administered ethernet addresses" generated by
- * ./tools/gen_eth_addr
- *
- * After booting the board for the first time, new addresses should be
- * generated and assigned to the environment variables "ethaddr" and
- * "eth1addr".
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
*/
-#define CONFIG_ETHADDR 6a:87:71:14:cd:cb
-#define CONFIG_ETH1ADDR ca:f8:15:e6:3e:e6
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_BSP
#undef CONFIG_CMD_DCR
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_KGDB
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_VFD
#undef CONFIG_CMD_XIMG
-
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
#define CFG_DEFAULT_IMMR 0x00010000
/*
* Command line configuration.
*/
-#include <config_cmd_all.h>
-
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_BMP
-#undef CONFIG_CMD_DISPLAY
-#undef CONFIG_CMD_DOC
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_FDC
-#undef CONFIG_CMD_FDOS
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_HWFLOW
-#undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_MFSL
-#undef CONFIG_CMD_MMC
-#undef CONFIG_CMD_PCMCIA
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_REISER
-#undef CONFIG_CMD_SCSI
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_UNIVERSE
-#undef CONFIG_CMD_VFD
#undef CONFIG_CMD_XIMG
-
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#include <image.h>
#include <zlib.h>
#include <bzlib.h>
+#include <watchdog.h>
#include <environment.h>
#include <asm/byteorder.h>
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
+#define CHUNKSZ (64 * 1024)
+
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
+
+#
+# From Linux arch/mips/Makefile
+#
+# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
+# code since it only slows down the whole thing. At some point we might make
+# use of global pointer optimizations but their use of $28 conflicts with
+# the current pointer optimization.
+#
+# The DECStation requires an ECOFF kernel for remote booting, other MIPS
+# machines may also. Since BFD is incredibly buggy with respect to
+# crossformat linking we rely on the elf2ecoff tool for format conversion.
+#
+# cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
+# cflags-y += -msoft-float
+# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
+# MODFLAGS += -mlong-calls
+#
+
+#
+# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly.
+#
+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -pipe
+PLATFORM_CPPFLAGS += -msoft-float
+PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
bp->bp_hlen = HWL_ETHER;
bp->bp_hops = 0;
bp->bp_secs = htons(get_timer(0) / CFG_HZ);
- NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */
- NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr);
- NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr);
+ /* Do not set the client IP, your IP, or server IP yet, since it hasn't been ACK'ed by
+ * the server yet */
+
/*
* RFC3046 requires Relay Agents to discard packets with
* nonzero and offered giaddr
/*
* Copy options from OFFER packet if present
*/
- NetCopyIP(&OfferedIP, &bp->bp_yiaddr);
+
+ /* Copy offered IP into the parameters request list */
+ NetCopyIP(&OfferedIP, &bp_offer->bp_yiaddr);
extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen;
{
BootpRequest();
}
-#endif
+#endif /* CONFIG_CMD_DHCP */
-#endif
+#endif /* CONFIG_CMD_NET */
if (rpc_pkt.u.reply.rstatus ||
rpc_pkt.u.reply.verifier ||
- rpc_pkt.u.reply.astatus ||
rpc_pkt.u.reply.astatus) {
return -1;
}
projects / karo-tx-uboot.git / commitdiff