ARM: dts: r8a7792: add MSIOF clocks

Describe the MSIOF0/1 clocks and their parent, MP clock in the R8A7792
device  tree.

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 713141d38b3ea960fcee7dfdbd9317bbc0527536..839cd70c4c75b26d6d2c38917c7e641a8349a713 100644 (file)
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -763,6 +763,13 @@
                        clock-div = <48>;
                        clock-mult = <1>;
                };
+               mp_clk: mp {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&pll1_div2_clk>;
+                       #clock-cells = <0>;
+                       clock-div = <15>;
+                       clock-mult = <1>;
+               };
                m2_clk: m2 {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
@@ -793,6 +800,15 @@
                };
 
                /* Gate clocks */
+               mstp0_clks: mstp0_clks@e6150130 {
+                       compatible = "renesas,r8a7792-mstp-clocks",
+                                    "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                       clocks = <&mp_clk>;
+                       #clock-cells = <1>;
+                       clock-indices = <R8A7792_CLK_MSIOF0>;
+                       clock-output-names = "msiof0";
+               };
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7792-mstp-clocks",
                                     "renesas,cpg-mstp-clocks";
@@ -811,12 +827,13 @@
                        compatible = "renesas,r8a7792-mstp-clocks",
                                     "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
-                       clocks = <&zs_clk>, <&zs_clk>;
+                       clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
+                               R8A7792_CLK_MSIOF1
                                R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
                        >;
-                       clock-output-names = "sys-dmac1", "sys-dmac0";
+                       clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
                };
                mstp3_clks: mstp3_clks@e615013c {
                        compatible = "renesas,r8a7792-mstp-clocks",