Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 TLB detection update from Ingo Molnar:
 "A single change that extends our TLB cache size detection+reporting
  code"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, cpu: Detect more TLB configuration

diff --combined arch/x86/include/asm/processor.h
index 613899651b026374e4aa4248b7ab33af127856e1,1dd6260ed940016d8d7f8d2387ae201b42a0be48..a61b0717da3210db336919c9215c1ef01dee9e6d
--- 1/arch/x86/include/asm/processor.h
--- 2/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@@ -27,6 -27,7 +27,6 @@@ struct mm_struct
  #include <linux/cache.h>
  #include <linux/threads.h>
  #include <linux/math64.h>
 -#include <linux/init.h>
  #include <linux/err.h>
  #include <linux/irqflags.h>
  
@@@ -71,6 -72,7 +71,7 @@@ extern u16 __read_mostly tlb_lli_4m[NR_
  extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  extern u16 __read_mostly tlb_lld_4m[NR_INFO];
+ extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  extern s8  __read_mostly tlb_flushall_shift;
  
  /*
@@@ -699,6 -701,29 +700,6 @@@ static inline void sync_core(void
  #endif
  }
  
 -static inline void __monitor(const void *eax, unsigned long ecx,
 -                           unsigned long edx)
 -{
 -      /* "monitor %eax, %ecx, %edx;" */
 -      asm volatile(".byte 0x0f, 0x01, 0xc8;"
 -                   :: "a" (eax), "c" (ecx), "d"(edx));
 -}
 -
 -static inline void __mwait(unsigned long eax, unsigned long ecx)
 -{
 -      /* "mwait %eax, %ecx;" */
 -      asm volatile(".byte 0x0f, 0x01, 0xc9;"
 -                   :: "a" (eax), "c" (ecx));
 -}
 -
 -static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 -{
 -      trace_hardirqs_on();
 -      /* "mwait %eax, %ecx;" */
 -      asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 -                   :: "a" (eax), "c" (ecx));
 -}
 -
  extern void select_idle_routine(const struct cpuinfo_x86 *c);
  extern void init_amd_e400_c1e_mask(void);
  

diff --combined arch/x86/kernel/cpu/intel.c
index 3004eca83b92ce4cf0c211242b2b2adb8425dc3b,5eb7ea5fae15eb38c1f1e525dc038e2f7aae69f6..3db61c644e440e8af7b978320b546a25336055f4
--- 1/arch/x86/kernel/cpu/intel.c
--- 2/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@@ -1,3 -1,4 +1,3 @@@
 -#include <linux/init.h>
  #include <linux/kernel.h>
  
  #include <linux/string.h>
@@@ -92,7 -93,7 +92,7 @@@ static void early_init_intel(struct cpu
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
                set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
                if (!check_tsc_unstable())
 -                      sched_clock_stable = 1;
 +                      set_sched_clock_stable();
        }
  
        /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
@@@ -505,6 -506,7 +505,7 @@@ static unsigned int intel_size_cache(st
  #define TLB_DATA0_2M_4M       0x23
  
  #define STLB_4K               0x41
+ #define STLB_4K_2M    0x42
  
  static const struct _tlb_table intel_tlb_table[] = {
        { 0x01, TLB_INST_4K,            32,     " TLB_INST 4 KByte pages, 4-way set associative" },
@@@ -525,13 -527,20 +526,20 @@@
        { 0x5b, TLB_DATA_4K_4M,         64,     " TLB_DATA 4 KByte and 4 MByte pages" },
        { 0x5c, TLB_DATA_4K_4M,         128,    " TLB_DATA 4 KByte and 4 MByte pages" },
        { 0x5d, TLB_DATA_4K_4M,         256,    " TLB_DATA 4 KByte and 4 MByte pages" },
+       { 0x61, TLB_INST_4K,            48,     " TLB_INST 4 KByte pages, full associative" },
+       { 0x63, TLB_DATA_1G,            4,      " TLB_DATA 1 GByte pages, 4-way set associative" },
+       { 0x76, TLB_INST_2M_4M,         8,      " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
        { 0xb0, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 4-way set associative" },
        { 0xb1, TLB_INST_2M_4M,         4,      " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
        { 0xb2, TLB_INST_4K,            64,     " TLB_INST 4KByte pages, 4-way set associative" },
        { 0xb3, TLB_DATA_4K,            128,    " TLB_DATA 4 KByte pages, 4-way set associative" },
        { 0xb4, TLB_DATA_4K,            256,    " TLB_DATA 4 KByte pages, 4-way associative" },
+       { 0xb5, TLB_INST_4K,            64,     " TLB_INST 4 KByte pages, 8-way set ssociative" },
+       { 0xb6, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 8-way set ssociative" },
        { 0xba, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way associative" },
        { 0xc0, TLB_DATA_4K_4M,         8,      " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
+       { 0xc1, STLB_4K_2M,             1024,   " STLB 4 KByte and 2 MByte pages, 8-way associative" },
+       { 0xc2, TLB_DATA_2M_4M,         16,     " DTLB 2 MByte/4MByte pages, 4-way associative" },
        { 0xca, STLB_4K,                512,    " STLB 4 KByte pages, 4-way associative" },
        { 0x00, 0, 0 }
  };
@@@ -557,6 -566,20 +565,20 @@@ static void intel_tlb_lookup(const unsi
                if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
                        tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
                break;
+       case STLB_4K_2M:
+               if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
+                       tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
+               if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
+                       tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
+               if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
+                       tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
+               if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
+                       tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
+               if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
+                       tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+               if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
+                       tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+               break;
        case TLB_INST_ALL:
                if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
                        tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
@@@ -601,6 -624,10 +623,10 @@@
                        tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
                if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
                        tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+               break;
+       case TLB_DATA_1G:
+               if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
+                       tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
                break;
        }
  }