Merge branch 'x86/cleanups' into irq/sparseirq

Reason: Avoid conflicts with removal of boot_cpu_id

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --combined arch/x86/kernel/apic/io_apic.c
index fe92916acd2a01e0a4e9a7ba4f8d548f59190c64,8884928d7bc1b052b5f492dc394fabcfc7230dd1..bc0fa1ae52339940529c8b80150958845aa6ada2
--- 1/arch/x86/kernel/apic/io_apic.c
--- 2/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@@ -162,7 -162,7 +162,7 @@@ int __init arch_early_irq_init(void
  
        cfg = irq_cfgx;
        count = ARRAY_SIZE(irq_cfgx);
-       node= cpu_to_node(boot_cpu_id);
+       node = cpu_to_node(0);
  
        for (i = 0; i < count; i++) {
                desc = irq_to_desc(i);
@@@ -1377,7 -1377,21 +1377,7 @@@ int setup_ioapic_entry(int apic_id, in
                if (index < 0)
                        panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
  
 -              memset(&irte, 0, sizeof(irte));
 -
 -              irte.present = 1;
 -              irte.dst_mode = apic->irq_dest_mode;
 -              /*
 -               * Trigger mode in the IRTE will always be edge, and the
 -               * actual level or edge trigger will be setup in the IO-APIC
 -               * RTE. This will help simplify level triggered irq migration.
 -               * For more details, see the comments above explainig IO-APIC
 -               * irq migration in the presence of interrupt-remapping.
 -               */
 -              irte.trigger_mode = 0;
 -              irte.dlvry_mode = apic->irq_delivery_mode;
 -              irte.vector = vector;
 -              irte.dest_id = IRTE_DEST(destination);
 +              prepare_irte(&irte, vector, destination);
  
                /* Set source-id of interrupt request */
                set_ioapic_sid(&irte, apic_id);
@@@ -1469,7 -1483,7 +1469,7 @@@ static void __init setup_IO_APIC_irqs(v
        int notcon = 0;
        struct irq_desc *desc;
        struct irq_cfg *cfg;
-       int node = cpu_to_node(boot_cpu_id);
+       int node = cpu_to_node(0);
  
        apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
  
@@@ -1534,7 -1548,7 +1534,7 @@@
  void setup_IO_APIC_irq_extra(u32 gsi)
  {
        int apic_id = 0, pin, idx, irq;
-       int node = cpu_to_node(boot_cpu_id);
+       int node = cpu_to_node(0);
        struct irq_desc *desc;
        struct irq_cfg *cfg;
  
@@@ -1714,8 -1728,6 +1714,8 @@@ __apicdebuginit(void) print_IO_APIC(voi
                struct irq_pin_list *entry;
  
                cfg = desc->chip_data;
 +              if (!cfg)
 +                      continue;
                entry = cfg->irq_2_pin;
                if (!entry)
                        continue;
@@@ -2913,7 -2925,7 +2913,7 @@@ static inline void __init check_timer(v
  {
        struct irq_desc *desc = irq_to_desc(0);
        struct irq_cfg *cfg = desc->chip_data;
-       int node = cpu_to_node(boot_cpu_id);
+       int node = cpu_to_node(0);
        int apic1, pin1, apic2, pin2;
        unsigned long flags;
        int no_pin1 = 0;
@@@ -3267,7 -3279,7 +3267,7 @@@ unsigned int create_irq_nr(unsigned in
  
  int create_irq(void)
  {
-       int node = cpu_to_node(boot_cpu_id);
+       int node = cpu_to_node(0);
        unsigned int irq_want;
        int irq;
  
@@@ -3321,7 -3333,14 +3321,7 @@@ static int msi_compose_msg(struct pci_d
                ir_index = map_irq_to_irte_handle(irq, &sub_handle);
                BUG_ON(ir_index == -1);
  
 -              memset (&irte, 0, sizeof(irte));
 -
 -              irte.present = 1;
 -              irte.dst_mode = apic->irq_dest_mode;
 -              irte.trigger_mode = 0; /* edge */
 -              irte.dlvry_mode = apic->irq_delivery_mode;
 -              irte.vector = cfg->vector;
 -              irte.dest_id = IRTE_DEST(dest);
 +              prepare_irte(&irte, cfg->vector, dest);
  
                /* Set source-id of interrupt request */
                if (pdev)
@@@ -3859,7 -3878,7 +3859,7 @@@ int __init arch_probe_nr_irqs(void
        if (nr < nr_irqs)
                nr_irqs = nr;
  
 -      return 0;
 +      return NR_IRQS_LEGACY;
  }
  #endif
  
@@@ -3882,7 -3901,7 +3882,7 @@@ static int __io_apic_set_pci_routing(st
        if (dev)
                node = dev_to_node(dev);
        else
-               node = cpu_to_node(boot_cpu_id);
+               node = cpu_to_node(0);
  
        desc = irq_to_desc_alloc_node(irq, node);
        if (!desc) {

diff --combined arch/x86/kernel/cpu/amd.c
index ba5f62f45f01e136e849894076917684ffcd8c40,3a7c852f021d24bbc7509c54095d8d2295dec3f3..a8b4d91b8394d5cd6d9ebc19106f9fa426330b78
--- 1/arch/x86/kernel/cpu/amd.c
--- 2/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@@ -148,7 -148,7 +148,7 @@@ static void __cpuinit amd_k7_smp_check(
  {
  #ifdef CONFIG_SMP
        /* calling is from identify_secondary_cpu() ? */
-       if (c->cpu_index == boot_cpu_id)
+       if (!c->cpu_index)
                return;
  
        /*
@@@ -669,7 -669,7 +669,7 @@@ bool cpu_has_amd_erratum(const int *err
        }
  
        /* OSVW unavailable or ID unknown, match family-model-stepping range */
 -      ms = (cpu->x86_model << 8) | cpu->x86_mask;
 +      ms = (cpu->x86_model << 4) | cpu->x86_mask;
        while ((range = *erratum++))
                if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
                    (ms >= AMD_MODEL_RANGE_START(range)) &&

diff --combined arch/x86/kernel/early-quirks.c
index ebdb85cf2686fa36702cd4d50b657f22de85b3bd,e4bd78c160d89761f4ce2457447d7a5ee58789e6..76b8cd953deed9f8a50d572cdc52b5edb68bc3b7
--- 1/arch/x86/kernel/early-quirks.c
--- 2/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@@ -18,6 -18,7 +18,6 @@@
  #include <asm/apic.h>
  #include <asm/iommu.h>
  #include <asm/gart.h>
 -#include <asm/hpet.h>
  
  static void __init fix_hypertransport_config(int num, int slot, int func)
  {
@@@ -96,7 -97,6 +96,6 @@@ static void __init nvidia_bugs(int num
  
  }
  
- #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
  #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
  static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
  {
@@@ -115,7 -115,6 +114,6 @@@
        d &= 0xff;
        return d;
  }
- #endif
  
  static void __init ati_bugs(int num, int slot, int func)
  {
@@@ -191,6 -190,21 +189,6 @@@ static void __init ati_bugs_contd(int n
  }
  #endif
  
 -/*
 - * Force the read back of the CMP register in hpet_next_event()
 - * to work around the problem that the CMP register write seems to be
 - * delayed. See hpet_next_event() for details.
 - *
 - * We do this on all SMBUS incarnations for now until we have more
 - * information about the affected chipsets.
 - */
 -static void __init ati_hpet_bugs(int num, int slot, int func)
 -{
 -#ifdef CONFIG_HPET_TIMER
 -      hpet_readback_cmp = 1;
 -#endif
 -}
 -
  #define QFLAG_APPLY_ONCE      0x1
  #define QFLAG_APPLIED         0x2
  #define QFLAG_DONE            (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@@ -220,6 -234,8 +218,6 @@@ static struct chipset early_qrk[] __ini
          PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
          PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
 -      { PCI_VENDOR_ID_ATI, PCI_ANY_ID,
 -        PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
        {}
  };
  

diff --combined arch/x86/kernel/setup.c
index c3a4fbb2b996d00277d6523cb76b74e2c5944621,dede5c4bae4b74d3f61d4d91ad45448e84434e2d..7d5ee08c982dc588e5f4c7c3e16c033d2244dcd4
--- 1/arch/x86/kernel/setup.c
--- 2/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@@ -125,7 -125,6 +125,6 @@@ unsigned long max_pfn_mapped
  RESERVE_BRK(dmi_alloc, 65536);
  #endif
  
- unsigned int boot_cpu_id __read_mostly;
  
  static __initdata unsigned long _brk_start = (unsigned long)__brk_base;
  unsigned long _brk_end = (unsigned long)__brk_base;
@@@ -1014,8 -1013,6 +1013,8 @@@ void __init setup_arch(char **cmdline_p
        paging_init();
        x86_init.paging.pagetable_setup_done(swapper_pg_dir);
  
 +      setup_trampoline_page_table();
 +
        tboot_probe();
  
  #ifdef CONFIG_X86_64