ENGR00230538-2: CAAM: Add Secure Memory and SNVS properties

Add Secure Memory and SNVS properties to MX6 configuration.

Previous configurations of MX6 platform device definition lacked
specific propeties for CAAM Secure Memory and SNVS. Added these
properties to define register ranges for both entities.

Also corrected the name for the offset of the address range for
CAAM Secure Memory to more accurately reflect it's purpose.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>

diff --git a/arch/arm/plat-mxc/devices/platform-imx-caam.c b/arch/arm/plat-mxc/devices/platform-imx-caam.c
index 316249032a8d5b71d8b8351375bdd9c297bd4740..aaaf501f179c105aa92724af40e9917c43968436 100644 (file)
--- a/arch/arm/plat-mxc/devices/platform-imx-caam.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-caam.c
@@ -31,6 +31,8 @@
 
 const struct imx_caam_data imx6q_imx_caam_data __initconst = {
        .iobase_caam = MXC_CAAM_BASE_ADDR,
+       .iobase_caam_sm = CAAM_SECMEM_BASE_ADDR,
+       .iobase_snvs = MX6Q_SNVS_BASE_ADDR,
        .irq_sec_vio = MXC_INT_SNVS_SEC,
        .irq_snvs = MX6Q_INT_SNVS,
        .jr[0].offset_jr = 0x1000,
@@ -50,6 +52,18 @@ struct platform_device *__init imx_add_caam(
                        .start = data->iobase_caam,
                        .end = data->iobase_caam + SZ_64K - 1,
                        .flags = IORESOURCE_MEM,
+               }, {
+                       /* Define range for secure memory */
+                       .name = "iobase_caam_sm",
+                       .start = data->iobase_caam_sm,
+                       .end = data->iobase_caam_sm + SZ_16K - 1,
+                       .flags = IORESOURCE_MEM,
+               }, {
+                       /* Define range for SNVS */
+                       .name = "iobase_snvs",
+                       .start = data->iobase_snvs,
+                       .end = data->iobase_snvs + SZ_4K - 1,
+                       .flags = IORESOURCE_MEM,
                }, {
                        /* Define interrupt for security violations */
                        .name = "irq_sec_vio",

diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 1ff68bd8b6dd45b705e95c66790bc7a8132a74f4..f6d616d0b98acfbec7b9b3b99bcdd0c0f31ed804 100755 (executable)
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -112,9 +112,11 @@ struct imx_caam_jr_data {
 };
 
 struct imx_caam_data {
-       resource_size_t iobase_caam;
-       resource_size_t irq_sec_vio;
-       resource_size_t irq_snvs;
+       resource_size_t iobase_caam;    /* entirety of CAAM register map */
+       resource_size_t iobase_caam_sm; /* base of secure memory */
+       resource_size_t iobase_snvs;    /* base of SNVS */
+       resource_size_t irq_sec_vio;    /* SNVS security violation */
+       resource_size_t irq_snvs;       /* SNVS consolidated (incl. RTC) */
        struct imx_caam_jr_data jr[4];  /* offset+IRQ for each possible ring */
 };
 

diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h
index dfb3f6489cc1aece1de1b93fcf633e687ce343b0..48b04b1045603f0a54e1ab337f35a1ffcd746d02 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx6.h
+++ b/arch/arm/plat-mxc/include/mach/mx6.h
@@ -83,8 +83,8 @@
 #define ROMCP_ARB_BASE_ADDR            0x00000000
 #define ROMCP_ARB_END_ADDR             0x000FFFFF
 #define BOOT_ROM_BASE_ADDR             ROMCP_ARB_BASE_ADDR
-#define CAAM_ARB_BASE_ADDR             0x00100000
-#define CAAM_ARB_END_ADDR              0x00103FFF
+#define CAAM_SECMEM_BASE_ADDR          0x00100000
+#define CAAM_SECMEM_END_ADDR           0x00103FFF
 #define APBH_DMA_ARB_BASE_ADDR         0x00110000
 #define APBH_DMA_ARB_END_ADDR          0x00117FFF
 #define MX6Q_HDMI_ARB_BASE_ADDR                0x00120000