Merge branches 'amba', 'fixes', 'gpio', 'io' (early part), 'p2v' and 'pgt' into for...

diff --cc arch/arm/Kconfig
index 3269576dbfa8dab12d6531996e2e86de2ca309c1,5ebc5d922ea14984e10ef8e10f47d414469efa7c,3146ed3f6eca01a42068454e31f53a3330cc12c6,05589e85c1804d481a6f84e058c9b0e096677d73,2c71a8f3535a1400c2d187e7fa612e00995e6927,272eadc7a12cc552497dd3ad437c0ed76f7438a1,5ebc5d922ea14984e10ef8e10f47d414469efa7c..56006d75b5aa89851cd24bfbc92590687c1d53e1
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
--- 3/arch/arm/Kconfig
--- 4/arch/arm/Kconfig
--- 5/arch/arm/Kconfig
--- 6/arch/arm/Kconfig
--- 7/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@@@@@@ -195,7 -195,7 -195,7 -195,8 -195,8 -195,8 -195,7 +195,8 @@@@@@@@ config VECTORS_BAS
          The base address of exception vectors.
       
       config ARM_PATCH_PHYS_VIRT
---   - bool "Patch physical to virtual translations at runtime"
   --   bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
   --   depends on EXPERIMENTAL
+++++ + bool "Patch physical to virtual translations at runtime" if EMBEDDED
+++++ + default y
        depends on !XIP_KERNEL && MMU
        depends on !ARCH_REALVIEW || !SPARSEMEM
        help
@@@@@@@@ -1271,18 -1271,6 -1271,32 -1273,6 -1272,6 -1267,6 -1271,6 +1268,32 @@@@@@@@ config ARM_ERRATA_75432
          This workaround defines cpu_relax() as smp_mb(), preventing correctly
          written polling loops from denying visibility of updates to memory.
       
 + ++++config ARM_ERRATA_364296
 + ++++ bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
 + ++++ depends on CPU_V6 && !SMP
 + ++++ help
 + ++++   This options enables the workaround for the 364296 ARM1136
 + ++++   r0p2 erratum (possible cache data corruption with
 + ++++   hit-under-miss enabled). It sets the undocumented bit 31 in
 + ++++   the auxiliary control register and the FI bit in the control
 + ++++   register, thus disabling hit-under-miss without putting the
 + ++++   processor into full low interrupt latency mode. ARM11MPCore
 + ++++   is not affected.
 + ++++
++ ++++config ARM_ERRATA_764369
++ ++++ bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
++ ++++ depends on CPU_V7 && SMP
++ ++++ help
++ ++++   This option enables the workaround for erratum 764369
++ ++++   affecting Cortex-A9 MPCore with two or more processors (all
++ ++++   current revisions). Under certain timing circumstances, a data
++ ++++   cache line maintenance operation by MVA targeting an Inner
++ ++++   Shareable memory region may fail to proceed up to either the
++ ++++   Point of Coherency or to the Point of Unification of the
++ ++++   system. This workaround adds a DSB instruction before the
++ ++++   relevant cache maintenance functions and sets a specific bit
++ ++++   in the diagnostic control register of the SCU.
++ ++++
       endmenu
       
       source "arch/arm/common/Kconfig"

diff --cc arch/arm/kernel/head.S
Simple merge

diff --cc arch/arm/mach-msm/board-msm7x30.c
Simple merge

diff --cc arch/arm/mach-orion5x/dns323-setup.c
Simple merge

diff --cc arch/arm/mm/dma-mapping.c
Simple merge

diff --cc drivers/tty/serial/atmel_serial.c
Simple merge