* PCI bar 1 register I/O map
*/
#define APCI3501_AO_CTRL_STATUS_REG 0x00
-#define APCI3501_AO_CTRL_BIPOLAR (1 << 0)
-#define APCI3501_AO_STATUS_READY (1 << 8)
+#define APCI3501_AO_CTRL_BIPOLAR BIT(0)
+#define APCI3501_AO_STATUS_READY BIT(8)
#define APCI3501_AO_DATA_REG 0x04
#define APCI3501_AO_DATA_CHAN(x) ((x) << 0)
#define APCI3501_AO_DATA_VAL(x) ((x) << 8)
-#define APCI3501_AO_DATA_BIPOLAR (1 << 31)
+#define APCI3501_AO_DATA_BIPOLAR BIT(31)
#define APCI3501_AO_TRIG_SCS_REG 0x08
#define APCI3501_TIMER_SYNC_REG 0x20
#define APCI3501_TIMER_RELOAD_REG 0x24