.dev.platform_data = m520x_uart_platform,
};
+static struct resource m520x_fec_resources[] = {
+ {
+ .start = MCF_MBAR + 0x30000,
+ .end = MCF_MBAR + 0x30000 + 0x7ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 64 + 36,
+ .end = 64 + 36,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 40,
+ .end = 64 + 40,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 42,
+ .end = 64 + 42,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device m520x_fec = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(m520x_fec_resources),
+ .resource = m520x_fec_resources,
+};
+
static struct platform_device *m520x_devices[] __initdata = {
&m520x_uart,
+ &m520x_fec,
};
/***************************************************************************/
/***************************************************************************/
+static void __init m520x_fec_init(void)
+{
+ u32 imr;
+ u8 v;
+
+ /* Unmask FEC interrupts at ColdFire interrupt controller */
+ writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 36);
+ writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40);
+ writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42);
+
+ imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
+ imr &= ~0x0001FFF0;
+ writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
+
+ /* Set multi-function pins to ethernet mode */
+ v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
+ writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
+
+ v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
+ writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
+}
+
+/***************************************************************************/
+
/*
* Program the vector to be an auto-vectored.
*/
{
mach_reset = coldfire_reset;
m520x_uarts_init();
+ m520x_fec_init();
}
/***************************************************************************/
.dev.platform_data = m523x_uart_platform,
};
+static struct resource m523x_fec_resources[] = {
+ {
+ .start = MCF_MBAR + 0x1000,
+ .end = MCF_MBAR + 0x1000 + 0x7ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 64 + 23,
+ .end = 64 + 23,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 27,
+ .end = 64 + 27,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 29,
+ .end = 64 + 29,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device m523x_fec = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(m523x_fec_resources),
+ .resource = m523x_fec_resources,
+};
+
static struct platform_device *m523x_devices[] __initdata = {
&m523x_uart,
+ &m523x_fec,
};
/***************************************************************************/
/***************************************************************************/
+static void __init m523x_fec_init(void)
+{
+ u32 imr;
+
+ /* Unmask FEC interrupts at ColdFire interrupt controller */
+ writeb(0x28, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 23);
+ writeb(0x27, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 27);
+ writeb(0x26, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 29);
+
+ imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
+ imr &= ~0xf;
+ writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
+ imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
+ imr &= ~0xff800001;
+ writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
+}
+
+/***************************************************************************/
+
void mcf_disableall(void)
{
*((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
mcf_disableall();
mach_reset = coldfire_reset;
m523x_uarts_init();
+ m523x_fec_init();
}
/***************************************************************************/
.dev.platform_data = m5272_uart_platform,
};
+static struct resource m5272_fec_resources[] = {
+ {
+ .start = MCF_MBAR + 0x840,
+ .end = MCF_MBAR + 0x840 + 0x1cf,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 86,
+ .end = 86,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 87,
+ .end = 87,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 88,
+ .end = 88,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device m5272_fec = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(m5272_fec_resources),
+ .resource = m5272_fec_resources,
+};
+
static struct platform_device *m5272_devices[] __initdata = {
&m5272_uart,
+ &m5272_fec,
};
/***************************************************************************/
/***************************************************************************/
+static void __init m5272_fec_init(void)
+{
+ u32 imr;
+
+ /* Unmask FEC interrupts at ColdFire interrupt controller */
+ imr = readl(MCF_MBAR + MCFSIM_ICR3);
+ imr = (imr & ~0x00000fff) | 0x00000ddd;
+ writel(imr, MCF_MBAR + MCFSIM_ICR3);
+
+ imr = readl(MCF_MBAR + MCFSIM_ICR1);
+ imr = (imr & ~0x0f000000) | 0x0d000000;
+ writel(imr, MCF_MBAR + MCFSIM_ICR1);
+}
+
+/***************************************************************************/
+
void mcf_disableall(void)
{
volatile unsigned long *icrp;
static int __init init_BSP(void)
{
m5272_uarts_init();
+ m5272_fec_init();
platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
return 0;
}
.dev.platform_data = m527x_uart_platform,
};
+static struct resource m527x_fec0_resources[] = {
+ {
+ .start = MCF_MBAR + 0x1000,
+ .end = MCF_MBAR + 0x1000 + 0x7ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 64 + 23,
+ .end = 64 + 23,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 27,
+ .end = 64 + 27,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 29,
+ .end = 64 + 29,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource m527x_fec1_resources[] = {
+ {
+ .start = MCF_MBAR + 0x1800,
+ .end = MCF_MBAR + 0x1800 + 0x7ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 128 + 23,
+ .end = 128 + 23,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 128 + 27,
+ .end = 128 + 27,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 128 + 29,
+ .end = 128 + 29,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device m527x_fec[] = {
+ {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(m527x_fec0_resources),
+ .resource = m527x_fec0_resources,
+ },
+ {
+ .name = "fec",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(m527x_fec1_resources),
+ .resource = m527x_fec1_resources,
+ },
+};
+
static struct platform_device *m527x_devices[] __initdata = {
&m527x_uart,
+ &m527x_fec[0],
+#ifdef CONFIG_FEC2
+ &m527x_fec[1],
+#endif
};
/***************************************************************************/
/***************************************************************************/
+static void __init m527x_fec_irq_init(int nr)
+{
+ unsigned long base;
+ u32 imr;
+
+ base = MCF_IPSBAR + (nr ? MCFICM_INTC1 : MCFICM_INTC0);
+
+ writeb(0x28, base + MCFINTC_ICR0 + 23);
+ writeb(0x27, base + MCFINTC_ICR0 + 27);
+ writeb(0x26, base + MCFINTC_ICR0 + 29);
+
+ imr = readl(base + MCFINTC_IMRH);
+ imr &= ~0xf;
+ writel(imr, base + MCFINTC_IMRH);
+ imr = readl(base + MCFINTC_IMRL);
+ imr &= ~0xff800001;
+ writel(imr, base + MCFINTC_IMRL);
+}
+
+static void __init m527x_fec_init(void)
+{
+ u16 par;
+ u8 v;
+
+ m527x_fec_irq_init(0);
+
+ /* Set multi-function pins to ethernet mode for fec0 */
+ par = readw(MCF_IPSBAR + 0x100082);
+ writew(par | 0xf00, MCF_IPSBAR + 0x100082);
+ v = readb(MCF_IPSBAR + 0x100078);
+ writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+
+#ifdef CONFIG_FEC2
+ m527x_fec_irq_init(1);
+
+ /* Set multi-function pins to ethernet mode for fec1 */
+ par = readw(MCF_IPSBAR + 0x100082);
+ writew(par | 0xa0, MCF_IPSBAR + 0x100082);
+ v = readb(MCF_IPSBAR + 0x100079);
+ writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+#endif
+}
+
+/***************************************************************************/
+
void mcf_disableall(void)
{
*((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
{
mcf_disableall();
mach_reset = coldfire_reset;
+ m527x_uarts_init();
+ m527x_fec_init();
}
/***************************************************************************/
static int __init init_BSP(void)
{
- m527x_uarts_init();
platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
return 0;
}
.dev.platform_data = m528x_uart_platform,
};
+static struct resource m528x_fec_resources[] = {
+ {
+ .start = MCF_MBAR + 0x1000,
+ .end = MCF_MBAR + 0x1000 + 0x7ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 64 + 23,
+ .end = 64 + 23,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 27,
+ .end = 64 + 27,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 29,
+ .end = 64 + 29,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device m528x_fec = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(m528x_fec_resources),
+ .resource = m528x_fec_resources,
+};
+
+
static struct platform_device *m528x_devices[] __initdata = {
&m528x_uart,
+ &m528x_fec,
};
/***************************************************************************/
/***************************************************************************/
+static void __init m528x_fec_init(void)
+{
+ u32 imr;
+ u16 v16;
+
+ /* Unmask FEC interrupts at ColdFire interrupt controller */
+ writeb(0x28, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 23);
+ writeb(0x27, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 27);
+ writeb(0x26, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 29);
+
+ imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
+ imr &= ~0xf;
+ writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
+ imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
+ imr &= ~0xff800001;
+ writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
+
+ /* Set multi-function pins to ethernet mode for fec0 */
+ v16 = readw(MCF_IPSBAR + 0x100056);
+ writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
+ writeb(0xc0, MCF_IPSBAR + 0x100058);
+}
+
+/***************************************************************************/
+
void mcf_disableall(void)
{
*((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
static int __init init_BSP(void)
{
m528x_uarts_init();
+ m528x_fec_init();
platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
return 0;
}
.dev.platform_data = m532x_uart_platform,
};
+static struct resource m532x_fec_resources[] = {
+ {
+ .start = 0xfc030000,
+ .end = 0xfc0307ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 64 + 36,
+ .end = 64 + 36,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 40,
+ .end = 64 + 40,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 64 + 42,
+ .end = 64 + 42,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device m532x_fec = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(m532x_fec_resources),
+ .resource = m532x_fec_resources,
+};
static struct platform_device *m532x_devices[] __initdata = {
&m532x_uart,
+ &m532x_fec,
};
/***************************************************************************/
for (line = 0; (line < nrlines); line++)
m532x_uart_init_line(line, m532x_uart_platform[line].irq);
}
+/***************************************************************************/
+
+static void __init m532x_fec_init(void)
+{
+ /* Unmask FEC interrupts at ColdFire interrupt controller */
+ MCF_INTC0_ICR36 = 0x2;
+ MCF_INTC0_ICR40 = 0x2;
+ MCF_INTC0_ICR42 = 0x2;
+
+ MCF_INTC0_IMRH &= ~(MCF_INTC_IMRH_INT_MASK36 |
+ MCF_INTC_IMRH_INT_MASK40 | MCF_INTC_IMRH_INT_MASK42);
+
+ /* Set multi-function pins to ethernet mode for fec0 */
+ MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
+ MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
+ MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
+ MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
+}
/***************************************************************************/
static int __init init_BSP(void)
{
m532x_uarts_init();
+ m532x_fec_init();
platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
return 0;
}
u_long flags;
spin_lock_irqsave(&timer->dev->lock, flags);
- list_del(&timer->list);
- list_add_tail(&timer->list, &timer->dev->expired);
+ list_move_tail(&timer->list, &timer->dev->expired);
spin_unlock_irqrestore(&timer->dev->lock, flags);
wake_up_interruptible(&timer->dev->wait);
}
#include <linux/delay.h>
-static char version[] __devinitdata =
-DRV_NAME ": Donald Becker and others.\n";
+static const char version[] __devinitconst =
+ DRV_NAME ": Donald Becker and others.\n";
MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
} else {
if (VORTEX_EISA(vp))
- sprintf(info->bus_info, dev_name(vp->gendev));
+ strcpy(info->bus_info, dev_name(vp->gendev));
else
sprintf(info->bus_info, "EISA 0x%lx %d",
dev->base_addr, dev->irq);
MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
-static char version[] __devinitdata =
+static const char version[] __devinitconst =
"acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
" http://home.cern.ch/~jes/gige/acenic.html\n";
#include <asm/byteorder.h>
/* These identify the driver base version and may not be removed. */
-static char version[] =
-KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
+static const char version[] __devinitconst =
+ KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
/* This driver was written to use PCI memory space, however some x86 systems
#define FEC_ALIGNMENT 0x3
#endif
-#if defined CONFIG_M5272 || defined CONFIG_M527x || defined CONFIG_M523x \
- || defined CONFIG_M528x || defined CONFIG_M532x || defined CONFIG_M520x
-#define FEC_LEGACY
/*
* Define the fixed address of the FEC hardware.
*/
#if defined(CONFIG_M5272)
#define HAVE_mii_link_interrupt
-#endif
-
-#if defined(CONFIG_FEC2)
-#define FEC_MAX_PORTS 2
-#else
-#define FEC_MAX_PORTS 1
-#endif
-
-static unsigned int fec_hw[] = {
-#if defined(CONFIG_M5272)
- (MCF_MBAR + 0x840),
-#elif defined(CONFIG_M527x)
- (MCF_MBAR + 0x1000),
- (MCF_MBAR + 0x1800),
-#elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
- (MCF_MBAR + 0x1000),
-#elif defined(CONFIG_M520x)
- (MCF_MBAR+0x30000),
-#elif defined(CONFIG_M532x)
- (MCF_MBAR+0xfc030000),
-#endif
-};
static unsigned char fec_mac_default[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
#else
#define FEC_FLASHMAC 0
#endif
-
-#endif /* FEC_LEGACY */
+#endif /* CONFIG_M5272 */
/* Forward declarations of some structures to support different PHYs
*/
#ifdef HAVE_mii_link_interrupt
static irqreturn_t
mii_link_interrupt(int irq, void * dev_id);
-#endif
-#if defined(CONFIG_M5272)
/*
- * Code specific to Coldfire 5272 setup.
+ * This is specific to the MII interrupt setup of the M5272EVB.
*/
-static void __inline__ fec_request_intrs(struct net_device *dev)
+static void __inline__ fec_request_mii_intr(struct net_device *dev)
{
- volatile unsigned long *icrp;
- static const struct idesc {
- char *name;
- unsigned short irq;
- irq_handler_t handler;
- } *idp, id[] = {
- { "fec(RX)", 86, fec_enet_interrupt },
- { "fec(TX)", 87, fec_enet_interrupt },
- { "fec(OTHER)", 88, fec_enet_interrupt },
- { "fec(MII)", 66, mii_link_interrupt },
- { NULL },
- };
-
- /* Setup interrupt handlers. */
- for (idp = id; idp->name; idp++) {
- if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
- printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
- }
-
- /* Unmask interrupt at ColdFire 5272 SIM */
- icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
- *icrp = 0x00000ddd;
- icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
- *icrp = 0x0d000000;
-}
-
-static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
-{
- volatile fec_t *fecp;
-
- fecp = fep->hwp;
- fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
- fecp->fec_x_cntrl = 0x00;
-
- /*
- * Set MII speed to 2.5 MHz
- * See 5272 manual section 11.5.8: MSCR
- */
- fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
- fecp->fec_mii_speed = fep->phy_speed;
-
- fec_restart(dev, 0);
-}
-
-static void __inline__ fec_get_mac(struct net_device *dev)
-{
- struct fec_enet_private *fep = netdev_priv(dev);
- volatile fec_t *fecp;
- unsigned char *iap, tmpaddr[ETH_ALEN];
-
- fecp = fep->hwp;
-
- if (FEC_FLASHMAC) {
- /*
- * Get MAC address from FLASH.
- * If it is all 1's or 0's, use the default.
- */
- iap = (unsigned char *)FEC_FLASHMAC;
- if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
- (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
- iap = fec_mac_default;
- if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
- (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
- iap = fec_mac_default;
- } else {
- *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
- *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
- iap = &tmpaddr[0];
- }
-
- memcpy(dev->dev_addr, iap, ETH_ALEN);
-
- /* Adjust MAC if using default MAC address */
- if (iap == fec_mac_default)
- dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
+ if (request_irq(66, mii_link_interrupt, IRQF_DISABLED, "fec(MII)", dev) != 0)
+ printk("FEC: Could not allocate fec(MII) IRQ(66)!\n");
}
static void __inline__ fec_disable_phy_intr(void)
*icrp = 0x0d000000;
}
-/* ------------------------------------------------------------------------- */
-
-#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-
-/*
- * Code specific to Coldfire 5230/5231/5232/5234/5235,
- * the 5270/5271/5274/5275 and 5280/5282 setups.
- */
-static void __inline__ fec_request_intrs(struct net_device *dev)
-{
- struct fec_enet_private *fep;
- int b;
- static const struct idesc {
- char *name;
- unsigned short irq;
- } *idp, id[] = {
- { "fec(TXF)", 23 },
- { "fec(RXF)", 27 },
- { "fec(MII)", 29 },
- { NULL },
- };
-
- fep = netdev_priv(dev);
- b = (fep->index) ? 128 : 64;
-
- /* Setup interrupt handlers. */
- for (idp = id; idp->name; idp++) {
- if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
- printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
- }
-
- /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
- {
- volatile unsigned char *icrp;
- volatile unsigned long *imrp;
- int i, ilip;
-
- b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
- icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
- MCFINTC_ICR0);
- for (i = 23, ilip = 0x28; (i < 36); i++)
- icrp[i] = ilip--;
-
- imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
- MCFINTC_IMRH);
- *imrp &= ~0x0000000f;
- imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
- MCFINTC_IMRL);
- *imrp &= ~0xff800001;
- }
-
-#if defined(CONFIG_M528x)
- /* Set up gpio outputs for MII lines */
- {
- volatile u16 *gpio_paspar;
- volatile u8 *gpio_pehlpar;
-
- gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
- gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
- *gpio_paspar |= 0x0f00;
- *gpio_pehlpar = 0xc0;
- }
-#endif
-
-#if defined(CONFIG_M527x)
- /* Set up gpio outputs for MII lines */
- {
- volatile u8 *gpio_par_fec;
- volatile u16 *gpio_par_feci2c;
-
- gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
- /* Set up gpio outputs for FEC0 MII lines */
- gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
-
- *gpio_par_feci2c |= 0x0f00;
- *gpio_par_fec |= 0xc0;
-
-#if defined(CONFIG_FEC2)
- /* Set up gpio outputs for FEC1 MII lines */
- gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
-
- *gpio_par_feci2c |= 0x00a0;
- *gpio_par_fec |= 0xc0;
-#endif /* CONFIG_FEC2 */
- }
-#endif /* CONFIG_M527x */
-}
-
-static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
-{
- volatile fec_t *fecp;
-
- fecp = fep->hwp;
- fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
- fecp->fec_x_cntrl = 0x00;
-
- /*
- * Set MII speed to 2.5 MHz
- * See 5282 manual section 17.5.4.7: MSCR
- */
- fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
- fecp->fec_mii_speed = fep->phy_speed;
-
- fec_restart(dev, 0);
-}
-
-static void __inline__ fec_get_mac(struct net_device *dev)
-{
- struct fec_enet_private *fep = netdev_priv(dev);
- volatile fec_t *fecp;
- unsigned char *iap, tmpaddr[ETH_ALEN];
-
- fecp = fep->hwp;
-
- if (FEC_FLASHMAC) {
- /*
- * Get MAC address from FLASH.
- * If it is all 1's or 0's, use the default.
- */
- iap = FEC_FLASHMAC;
- if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
- (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
- iap = fec_mac_default;
- if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
- (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
- iap = fec_mac_default;
- } else {
- *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
- *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
- iap = &tmpaddr[0];
- }
-
- memcpy(dev->dev_addr, iap, ETH_ALEN);
-
- /* Adjust MAC if using default MAC address */
- if (iap == fec_mac_default)
- dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
-}
-
-static void __inline__ fec_disable_phy_intr(void)
-{
-}
-
-static void __inline__ fec_phy_ack_intr(void)
-{
-}
-
-/* ------------------------------------------------------------------------- */
-
-#elif defined(CONFIG_M520x)
-
-/*
- * Code specific to Coldfire 520x
- */
-static void __inline__ fec_request_intrs(struct net_device *dev)
-{
- struct fec_enet_private *fep;
- int b;
- static const struct idesc {
- char *name;
- unsigned short irq;
- } *idp, id[] = {
- { "fec(TXF)", 23 },
- { "fec(RXF)", 27 },
- { "fec(MII)", 29 },
- { NULL },
- };
-
- fep = netdev_priv(dev);
- b = 64 + 13;
-
- /* Setup interrupt handlers. */
- for (idp = id; idp->name; idp++) {
- if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
- printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
- }
-
- /* Unmask interrupts at ColdFire interrupt controller */
- {
- volatile unsigned char *icrp;
- volatile unsigned long *imrp;
-
- icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
- MCFINTC_ICR0);
- for (b = 36; (b < 49); b++)
- icrp[b] = 0x04;
- imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
- MCFINTC_IMRH);
- *imrp &= ~0x0001FFF0;
- }
- *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
- *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
-}
-
-static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
-{
- volatile fec_t *fecp;
-
- fecp = fep->hwp;
- fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
- fecp->fec_x_cntrl = 0x00;
-
- /*
- * Set MII speed to 2.5 MHz
- * See 5282 manual section 17.5.4.7: MSCR
- */
- fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
- fecp->fec_mii_speed = fep->phy_speed;
-
- fec_restart(dev, 0);
-}
-
+#ifdef CONFIG_M5272
static void __inline__ fec_get_mac(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
* Get MAC address from FLASH.
* If it is all 1's or 0's, use the default.
*/
- iap = FEC_FLASHMAC;
- if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
- (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
- iap = fec_mac_default;
- if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
- (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
- iap = fec_mac_default;
- } else {
- *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
- *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
- iap = &tmpaddr[0];
- }
-
- memcpy(dev->dev_addr, iap, ETH_ALEN);
-
- /* Adjust MAC if using default MAC address */
- if (iap == fec_mac_default)
- dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
-}
-
-static void __inline__ fec_disable_phy_intr(void)
-{
-}
-
-static void __inline__ fec_phy_ack_intr(void)
-{
-}
-
-/* ------------------------------------------------------------------------- */
-
-#elif defined(CONFIG_M532x)
-/*
- * Code specific for M532x
- */
-static void __inline__ fec_request_intrs(struct net_device *dev)
-{
- struct fec_enet_private *fep;
- int b;
- static const struct idesc {
- char *name;
- unsigned short irq;
- } *idp, id[] = {
- { "fec(TXF)", 36 },
- { "fec(RXF)", 40 },
- { "fec(MII)", 42 },
- { NULL },
- };
-
- fep = netdev_priv(dev);
- b = (fep->index) ? 128 : 64;
-
- /* Setup interrupt handlers. */
- for (idp = id; idp->name; idp++) {
- if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
- printk("FEC: Could not allocate %s IRQ(%d)!\n",
- idp->name, b+idp->irq);
- }
-
- /* Unmask interrupts */
- MCF_INTC0_ICR36 = 0x2;
- MCF_INTC0_ICR37 = 0x2;
- MCF_INTC0_ICR38 = 0x2;
- MCF_INTC0_ICR39 = 0x2;
- MCF_INTC0_ICR40 = 0x2;
- MCF_INTC0_ICR41 = 0x2;
- MCF_INTC0_ICR42 = 0x2;
- MCF_INTC0_ICR43 = 0x2;
- MCF_INTC0_ICR44 = 0x2;
- MCF_INTC0_ICR45 = 0x2;
- MCF_INTC0_ICR46 = 0x2;
- MCF_INTC0_ICR47 = 0x2;
- MCF_INTC0_ICR48 = 0x2;
-
- MCF_INTC0_IMRH &= ~(
- MCF_INTC_IMRH_INT_MASK36 |
- MCF_INTC_IMRH_INT_MASK37 |
- MCF_INTC_IMRH_INT_MASK38 |
- MCF_INTC_IMRH_INT_MASK39 |
- MCF_INTC_IMRH_INT_MASK40 |
- MCF_INTC_IMRH_INT_MASK41 |
- MCF_INTC_IMRH_INT_MASK42 |
- MCF_INTC_IMRH_INT_MASK43 |
- MCF_INTC_IMRH_INT_MASK44 |
- MCF_INTC_IMRH_INT_MASK45 |
- MCF_INTC_IMRH_INT_MASK46 |
- MCF_INTC_IMRH_INT_MASK47 |
- MCF_INTC_IMRH_INT_MASK48 );
-
- /* Set up gpio outputs for MII lines */
- MCF_GPIO_PAR_FECI2C |= (0 |
- MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
- MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
- MCF_GPIO_PAR_FEC = (0 |
- MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
- MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
-}
-
-static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
-{
- volatile fec_t *fecp;
-
- fecp = fep->hwp;
- fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
- fecp->fec_x_cntrl = 0x00;
-
- /*
- * Set MII speed to 2.5 MHz
- */
- fep->phy_speed = (MCF_CLK / 3) / (2500000 * 2 ) * 2;
- fecp->fec_mii_speed = fep->phy_speed;
-
- fec_restart(dev, 0);
-}
-
-static void __inline__ fec_get_mac(struct net_device *dev)
-{
- struct fec_enet_private *fep = netdev_priv(dev);
- volatile fec_t *fecp;
- unsigned char *iap, tmpaddr[ETH_ALEN];
-
- fecp = fep->hwp;
-
- if (FEC_FLASHMAC) {
- /*
- * Get MAC address from FLASH.
- * If it is all 1's or 0's, use the default.
- */
- iap = FEC_FLASHMAC;
+ iap = (unsigned char *)FEC_FLASHMAC;
if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
(iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
iap = fec_mac_default;
/* Adjust MAC if using default MAC address */
if (iap == fec_mac_default)
- dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
-}
-
-static void __inline__ fec_disable_phy_intr(void)
-{
-}
-
-static void __inline__ fec_phy_ack_intr(void)
-{
+ dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
}
-
#endif
/* ------------------------------------------------------------------------- */
printk("FEC: No PHY device found.\n");
/* Disable external MII interface */
fecp->fec_mii_speed = fep->phy_speed = 0;
-#ifdef FREC_LEGACY
+#ifdef HAVE_mii_link_interrupt
fec_disable_phy_intr();
#endif
}
udelay(10);
/* Set the Ethernet address */
-#ifdef FEC_LEGACY
+#ifdef CONFIG_M5272
fec_get_mac(dev);
#else
{
fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t)
* RX_RING_SIZE;
-#ifdef FEC_LEGACY
- /* Install our interrupt handlers. This varies depending on
- * the architecture.
- */
- fec_request_intrs(dev);
+#ifdef HAVE_mii_link_interrupt
+ fec_request_mii_intr(dev);
#endif
fecp->fec_grp_hash_table_high = 0;
mii_free = mii_cmds;
/* setup MII interface */
-#ifdef FEC_LEGACY
- fec_set_mii(dev, fep);
-#else
fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
fecp->fec_x_cntrl = 0x00;
/ 2500000) / 2) & 0x3F) << 1;
fecp->fec_mii_speed = fep->phy_speed;
fec_restart(dev, 0);
-#endif
/* Clear and enable interrupts */
fecp->fec_ievent = 0xffc00000;
fecp->fec_mii_speed = fep->phy_speed;
}
-#ifdef FEC_LEGACY
-static int __init fec_enet_module_init(void)
-{
- struct net_device *dev;
- int i, err;
-
- printk("FEC ENET Version 0.2\n");
-
- for (i = 0; (i < FEC_MAX_PORTS); i++) {
- dev = alloc_etherdev(sizeof(struct fec_enet_private));
- if (!dev)
- return -ENOMEM;
- dev->base_addr = (unsigned long)fec_hw[i];
- err = fec_enet_init(dev, i);
- if (err) {
- free_netdev(dev);
- continue;
- }
- if (register_netdev(dev) != 0) {
- /* XXX: missing cleanup here */
- free_netdev(dev);
- return -EIO;
- }
-
- printk("%s: ethernet %pM\n", dev->name, dev->dev_addr);
- }
- return 0;
-}
-#else
-
static int __devinit
fec_probe(struct platform_device *pdev)
{
}
module_exit(fec_enet_cleanup);
-
-#endif /* FEC_LEGACY */
-
module_init(fec_enet_module_init);
MODULE_LICENSE("GPL");
delaymax -= delay;
if (delaymax < 0) {
if (msg)
- printk(msg);
+ printk("%s", msg);
return 1;
}
} while ((readl(base + offset) & mask) != target);
#include <asm/unaligned.h>
#include <asm/cache.h>
-static char version[] __devinitdata =
+static const char version[] __devinitconst =
KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"
KERN_INFO " Some modifications by Eric kasten <kasten@nscl.msu.edu>\n"
KERN_INFO " Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n";
#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
/* These identify the driver base version and may not be removed. */
-static char version[] __devinitdata =
+static const char version[] __devinitconst =
KERN_INFO DRV_NAME " dp8381x driver, version "
DRV_VERSION ", " DRV_RELDATE "\n"
KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
#include "8390.h"
/* These identify the driver base version and may not be removed. */
-static char version[] __devinitdata =
-KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " D. Becker/P. Gortmaker\n";
+static const char version[] __devinitconst =
+ KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE
+ " D. Becker/P. Gortmaker\n";
#if defined(__powerpc__)
#define inl_le(addr) le32_to_cpu(inl(addr))
bus->dev.parent = bus->parent;
bus->dev.class = &mdio_bus_class;
bus->dev.groups = NULL;
- dev_set_name(&bus->dev, bus->id);
+ dev_set_name(&bus->dev, "%s", bus->id);
err = device_register(&bus->dev);
if (err) {
} while (0)
#define QLGE_VENDOR_ID 0x1077
-#define QLGE_DEVICE_ID 0x8012
+#define QLGE_DEVICE_ID_8012 0x8012
#define MAX_CPUS 8
#define MAX_TX_RINGS MAX_CPUS
CSR_RP = (1 << 10),
CSR_CMD_PARM_SHIFT = 22,
CSR_CMD_NOP = 0x00000000,
- CSR_CMD_SET_RST = 0x1000000,
+ CSR_CMD_SET_RST = 0x10000000,
CSR_CMD_CLR_RST = 0x20000000,
CSR_CMD_SET_PAUSE = 0x30000000,
CSR_CMD_CLR_PAUSE = 0x40000000,
RX_SYMBOL_ERR = 0x00000370,
RX_MAC_ERR = 0x00000378,
RX_CTL_PKTS = 0x00000380,
- RX_PAUSE_PKTS = 0x00000384,
+ RX_PAUSE_PKTS = 0x00000388,
RX_64_PKTS = 0x00000390,
RX_65_TO_127_PKTS = 0x00000398,
RX_128_255_PKTS = 0x000003a0,
AEN_LINK_DOWN = 0x00008012,
AEN_IDC_CMPLT = 0x00008100,
AEN_IDC_REQ = 0x00008101,
+ AEN_IDC_EXT = 0x00008102,
+ AEN_DCBX_CHG = 0x00008110,
+ AEN_AEN_LOST = 0x00008120,
+ AEN_AEN_SFP_IN = 0x00008130,
+ AEN_AEN_SFP_OUT = 0x00008131,
AEN_FW_INIT_DONE = 0x00008400,
AEN_FW_INIT_FAIL = 0x00008401,
MB_CMD_MB_TEST = 0x00000006,
MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
MB_CMD_ABOUT_FW = 0x00000008,
+ MB_CMD_COPY_RISC_RAM = 0x0000000a,
MB_CMD_LOAD_RISC_RAM = 0x0000000b,
MB_CMD_DUMP_RISC_RAM = 0x0000000c,
MB_CMD_WRITE_RAM = 0x0000000d,
+ MB_CMD_INIT_RISC_RAM = 0x0000000e,
MB_CMD_READ_RAM = 0x0000000f,
MB_CMD_STOP_FW = 0x00000014,
MB_CMD_MAKE_SYS_ERR = 0x0000002a,
+ MB_CMD_WRITE_SFP = 0x00000030,
+ MB_CMD_READ_SFP = 0x00000031,
MB_CMD_INIT_FW = 0x00000060,
- MB_CMD_GET_INIT_CB = 0x00000061,
+ MB_CMD_GET_IFCB = 0x00000061,
MB_CMD_GET_FW_STATE = 0x00000069,
MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
- MB_WOL_DISABLE = 0x00000000,
- MB_WOL_MAGIC_PKT = 0x00000001,
- MB_WOL_FLTR = 0x00000002,
- MB_WOL_UCAST = 0x00000004,
- MB_WOL_MCAST = 0x00000008,
- MB_WOL_BCAST = 0x00000010,
- MB_WOL_LINK_UP = 0x00000020,
- MB_WOL_LINK_DOWN = 0x00000040,
+ MB_WOL_DISABLE = 0,
+ MB_WOL_MAGIC_PKT = (1 << 1),
+ MB_WOL_FLTR = (1 << 2),
+ MB_WOL_UCAST = (1 << 3),
+ MB_WOL_MCAST = (1 << 4),
+ MB_WOL_BCAST = (1 << 5),
+ MB_WOL_LINK_UP = (1 << 6),
+ MB_WOL_LINK_DOWN = (1 << 7),
MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
- MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
+ MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
- MB_CMD_CLEAR_WOL_MAGIC = 0x00000114, /* Wake On Lan Magic Packet */
+ MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
+ MB_CMD_SET_WOL_IMMED = 0x00000115,
MB_CMD_PORT_RESET = 0x00000120,
MB_CMD_SET_PORT_CFG = 0x00000122,
MB_CMD_GET_PORT_CFG = 0x00000123,
- MB_CMD_SET_ASIC_VOLTS = 0x00000130,
- MB_CMD_GET_SNS_DATA = 0x00000131, /* Temp and Volt Sense data. */
+ MB_CMD_GET_LINK_STS = 0x00000124,
/* Mailbox Command Status. */
MB_CMD_STS_GOOD = 0x00004000, /* Success. */
MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
- MB_CMD_STS_ERR = 0x00004005, /* Error. */
+ MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
+ MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
+ MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
+ MB_CMD_STS_ERR = 0x00004005, /* System Error. */
+ MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
};
struct mbox_params {
int out_count;
};
-struct flash_params {
+struct flash_params_8012 {
u8 dev_id_str[4];
__le16 size;
__le16 csum;
__le16 res;
};
+union flash_params {
+ struct flash_params_8012 flash_params_8012;
+};
/*
* doorbell space for the rx ring context
__le16 vlan_id; /* 12 bits */
#define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
#define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
+#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
__le16 reserved1;
__le32 reserved2[6];
#define Q_LEN_CPP_16 0x0001
#define Q_LEN_CPP_32 0x0002
#define Q_LEN_CPP_64 0x0003
+#define Q_LEN_CPP_512 0x0006
__le16 flags;
#define Q_PRI_SHIFT 1
#define Q_FLAGS_LC 0x1000
QL_DMA64 = (1 << 5),
QL_PROMISCUOUS = (1 << 6),
QL_ALLMULTI = (1 << 7),
+ QL_PORT_CFG = (1 << 8),
+ QL_CAM_RT_SET = (1 << 9),
};
/* link_status bit definitions */
enum {
- LOOPBACK_MASK = 0x00000700,
- LOOPBACK_PCS = 0x00000100,
- LOOPBACK_HSS = 0x00000200,
- LOOPBACK_EXT = 0x00000300,
- PAUSE_MASK = 0x000000c0,
- PAUSE_STD = 0x00000040,
- PAUSE_PRI = 0x00000080,
- SPEED_MASK = 0x00000038,
- SPEED_100Mb = 0x00000000,
- SPEED_1Gb = 0x00000008,
- SPEED_10Gb = 0x00000010,
- LINK_TYPE_MASK = 0x00000007,
- LINK_TYPE_XFI = 0x00000001,
- LINK_TYPE_XAUI = 0x00000002,
- LINK_TYPE_XFI_BP = 0x00000003,
- LINK_TYPE_XAUI_BP = 0x00000004,
- LINK_TYPE_10GBASET = 0x00000005,
+ STS_LOOPBACK_MASK = 0x00000700,
+ STS_LOOPBACK_PCS = 0x00000100,
+ STS_LOOPBACK_HSS = 0x00000200,
+ STS_LOOPBACK_EXT = 0x00000300,
+ STS_PAUSE_MASK = 0x000000c0,
+ STS_PAUSE_STD = 0x00000040,
+ STS_PAUSE_PRI = 0x00000080,
+ STS_SPEED_MASK = 0x00000038,
+ STS_SPEED_100Mb = 0x00000000,
+ STS_SPEED_1Gb = 0x00000008,
+ STS_SPEED_10Gb = 0x00000010,
+ STS_LINK_TYPE_MASK = 0x00000007,
+ STS_LINK_TYPE_XFI = 0x00000001,
+ STS_LINK_TYPE_XAUI = 0x00000002,
+ STS_LINK_TYPE_XFI_BP = 0x00000003,
+ STS_LINK_TYPE_XAUI_BP = 0x00000004,
+ STS_LINK_TYPE_10GBASET = 0x00000005,
+};
+
+/* link_config bit definitions */
+enum {
+ CFG_JUMBO_FRAME_SIZE = 0x00010000,
+ CFG_PAUSE_MASK = 0x00000060,
+ CFG_PAUSE_STD = 0x00000020,
+ CFG_PAUSE_PRI = 0x00000040,
+ CFG_DCBX = 0x00000010,
+ CFG_LOOPBACK_MASK = 0x00000007,
+ CFG_LOOPBACK_PCS = 0x00000002,
+ CFG_LOOPBACK_HSS = 0x00000004,
+ CFG_LOOPBACK_EXT = 0x00000006,
+ CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
+};
+
+struct nic_operations {
+
+ int (*get_flash) (struct ql_adapter *);
+ int (*port_initialize) (struct ql_adapter *);
};
/*
u32 mailbox_in;
u32 mailbox_out;
+ struct mutex mpi_mutex;
int tx_ring_size;
int rx_ring_size;
u32 port_init;
u32 link_status;
- struct flash_params flash;
+ union flash_params flash;
struct net_device_stats stats;
struct workqueue_struct *q_workqueue;
struct delayed_work asic_reset_work;
struct delayed_work mpi_reset_work;
struct delayed_work mpi_work;
+ struct nic_operations *nic_ops;
+ u16 device_id;
};
/*
ecmd->advertising = ADVERTISED_10000baseT_Full;
ecmd->autoneg = AUTONEG_ENABLE;
ecmd->transceiver = XCVR_EXTERNAL;
- if ((qdev->link_status & LINK_TYPE_MASK) == LINK_TYPE_10GBASET) {
+ if ((qdev->link_status & STS_LINK_TYPE_MASK) ==
+ STS_LINK_TYPE_10GBASET) {
ecmd->supported |= (SUPPORTED_TP | SUPPORTED_Autoneg);
ecmd->advertising |= (ADVERTISED_TP | ADVERTISED_Autoneg);
ecmd->port = PORT_TP;
NETIF_MSG_IFUP |
NETIF_MSG_RX_ERR |
NETIF_MSG_TX_ERR |
- NETIF_MSG_TX_QUEUED |
- NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
+/* NETIF_MSG_TX_QUEUED | */
+/* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
/* NETIF_MSG_PKTDATA | */
NETIF_MSG_HW | NETIF_MSG_WOL | 0;
MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
- {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
+ {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
/* required last entry */
{0,}
};
(addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
(addr[5]);
- QPRINTK(qdev, IFUP, INFO,
+ QPRINTK(qdev, IFUP, DEBUG,
"Adding %s address %pM"
" at index %d in the CAM.\n",
((type ==
}
+static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
+{
+ int status, i;
+ u16 csum = 0;
+ __le16 *flash = (__le16 *)&qdev->flash;
+
+ status = strncmp((char *)&qdev->flash, str, 4);
+ if (status) {
+ QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
+ return status;
+ }
+
+ for (i = 0; i < size; i++)
+ csum += le16_to_cpu(*flash++);
+
+ if (csum)
+ QPRINTK(qdev, IFUP, ERR,
+ "Invalid flash checksum, csum = 0x%.04x.\n", csum);
+
+ return csum;
+}
+
static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
{
int status = 0;
return status;
}
-static int ql_get_flash_params(struct ql_adapter *qdev)
+static int ql_get_8012_flash_params(struct ql_adapter *qdev)
{
int i;
int status;
__le32 *p = (__le32 *)&qdev->flash;
u32 offset = 0;
+ u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
/* Second function's parameters follow the first
* function's.
*/
if (qdev->func)
- offset = sizeof(qdev->flash) / sizeof(u32);
+ offset = size;
if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
return -ETIMEDOUT;
- for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
+ for (i = 0; i < size; i++, p++) {
status = ql_read_flash_word(qdev, i+offset, p);
if (status) {
QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
}
}
+
+ status = ql_validate_flash(qdev,
+ sizeof(struct flash_params_8012) / sizeof(u16),
+ "8012");
+ if (status) {
+ QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
+ status = -EINVAL;
+ goto exit;
+ }
+
+ if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
+ status = -EINVAL;
+ goto exit;
+ }
+
+ memcpy(qdev->ndev->dev_addr,
+ qdev->flash.flash_params_8012.mac_addr,
+ qdev->ndev->addr_len);
+
exit:
ql_sem_unlock(qdev, SEM_FLASH_MASK);
return status;
* This functionality may be done in the MPI firmware at a
* later date.
*/
-static int ql_port_initialize(struct ql_adapter *qdev)
+static int ql_8012_port_initialize(struct ql_adapter *qdev)
{
int status = 0;
u32 data;
QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
rx_ring->type);
}
- QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
+ QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
CFG_LCQ, rx_ring->cq_id);
if (err) {
QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
return err;
}
- QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
+ QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
return err;
}
(qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
set_bit(QL_MSIX_ENABLED, &qdev->flags);
qdev->intr_count = qdev->rx_ring_count;
- QPRINTK(qdev, IFUP, INFO,
+ QPRINTK(qdev, IFUP, DEBUG,
"MSI-X Enabled, got %d vectors.\n",
qdev->intr_count);
return;
if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
free_irq(qdev->msi_x_entry[i].vector,
&qdev->rx_ring[i]);
- QPRINTK(qdev, IFDOWN, ERR,
+ QPRINTK(qdev, IFDOWN, DEBUG,
"freeing msix interrupt %d.\n", i);
} else {
free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
- QPRINTK(qdev, IFDOWN, ERR,
+ QPRINTK(qdev, IFDOWN, DEBUG,
"freeing msi interrupt %d.\n", i);
}
}
i);
goto err_irq;
} else {
- QPRINTK(qdev, IFUP, INFO,
+ QPRINTK(qdev, IFUP, DEBUG,
"Hooked intr %d, queue type %s%s%s, with name %s.\n",
i,
qdev->rx_ring[i].type ==
get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
- QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
+ QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
if (status) {
QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
return status;
}
- QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
+ QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
return status;
}
}
}
- status = ql_port_initialize(qdev);
- if (status) {
- QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
- return status;
- }
+ /* Initialize the port and set the max framesize. */
+ status = qdev->nic_ops->port_initialize(qdev);
+ if (status) {
+ QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
+ return status;
+ }
/* Set up the MAC address and frame routing filter. */
status = ql_cam_route_initialize(qdev);
/* Start NAPI for the RSS queues. */
for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
- QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
+ QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
i);
napi_enable(&qdev->rx_ring[i].napi);
}
ql_cycle_adapter(qdev);
}
+static struct nic_operations qla8012_nic_ops = {
+ .get_flash = ql_get_8012_flash_params,
+ .port_initialize = ql_8012_port_initialize,
+};
+
+
static void ql_get_board_info(struct ql_adapter *qdev)
{
qdev->func =
qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
}
qdev->chip_rev_id = ql_read32(qdev, REV_ID);
+ qdev->device_id = qdev->pdev->device;
+ if (qdev->device_id == QLGE_DEVICE_ID_8012)
+ qdev->nic_ops = &qla8012_nic_ops;
}
static void ql_release_all(struct pci_dev *pdev)
goto err_out;
}
- ql_get_board_info(qdev);
qdev->ndev = ndev;
qdev->pdev = pdev;
+ ql_get_board_info(qdev);
qdev->msg_enable = netif_msg_init(debug, default_msg);
spin_lock_init(&qdev->hw_lock);
spin_lock_init(&qdev->stats_lock);
/* make sure the EEPROM is good */
- err = ql_get_flash_params(qdev);
+ err = qdev->nic_ops->get_flash(qdev);
if (err) {
dev_err(&pdev->dev, "Invalid FLASH.\n");
goto err_out;
}
- if (!is_valid_ether_addr(qdev->flash.mac_addr))
- goto err_out;
-
- memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
/* Set up the default ring sizes. */
INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
+ mutex_init(&qdev->mpi_mutex);
if (!cards_found) {
dev_info(&pdev->dev, "%s\n", DRV_STRING);
#include "qlge.h"
-static int ql_read_mbox_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
+int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
{
int status;
/* wait for reg to come ready */
return status;
}
+int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data)
+{
+ int status = 0;
+ /* wait for reg to come ready */
+ status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
+ if (status)
+ goto exit;
+ /* write the data to the data reg */
+ ql_write32(qdev, PROC_DATA, data);
+ /* trigger the write */
+ ql_write32(qdev, PROC_ADDR, reg);
+ /* wait for reg to come ready */
+ status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
+ if (status)
+ goto exit;
+exit:
+ return status;
+}
+
+int ql_soft_reset_mpi_risc(struct ql_adapter *qdev)
+{
+ int status;
+ status = ql_write_mpi_reg(qdev, 0x00001010, 1);
+ return status;
+}
+
static int ql_get_mb_sts(struct ql_adapter *qdev, struct mbox_params *mbcp)
{
int i, status;
return -EBUSY;
for (i = 0; i < mbcp->out_count; i++) {
status =
- ql_read_mbox_reg(qdev, qdev->mailbox_out + i,
+ ql_read_mpi_reg(qdev, qdev->mailbox_out + i,
&mbcp->mbox_out[i]);
if (status) {
QPRINTK(qdev, DRV, ERR, "Failed mailbox read.\n");
ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
}
+/* Process an async event and clear it unless it's an
+ * error condition.
+ * This can get called iteratively from the mpi_work thread
+ * when events arrive via an interrupt.
+ * It also gets called when a mailbox command is polling for
+ * it's completion. */
+static int ql_mpi_handler(struct ql_adapter *qdev, struct mbox_params *mbcp)
+{
+ int status;
+
+ /* Just get mailbox zero for now. */
+ mbcp->out_count = 1;
+ status = ql_get_mb_sts(qdev, mbcp);
+ if (status) {
+ QPRINTK(qdev, DRV, ERR,
+ "Could not read MPI, resetting ASIC!\n");
+ ql_queue_asic_error(qdev);
+ goto end;
+ }
+
+ switch (mbcp->mbox_out[0]) {
+
+ case AEN_LINK_UP:
+ ql_link_up(qdev, mbcp);
+ break;
+
+ case AEN_LINK_DOWN:
+ ql_link_down(qdev, mbcp);
+ break;
+
+ case AEN_FW_INIT_DONE:
+ ql_init_fw_done(qdev, mbcp);
+ break;
+
+ case MB_CMD_STS_GOOD:
+ break;
+
+ case AEN_FW_INIT_FAIL:
+ case AEN_SYS_ERR:
+ case MB_CMD_STS_ERR:
+ ql_queue_fw_error(qdev);
+ break;
+
+ default:
+ QPRINTK(qdev, DRV, ERR,
+ "Unsupported AE %.08x.\n", mbcp->mbox_out[0]);
+ /* Clear the MPI firmware status. */
+ }
+end:
+ ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
+ return status;
+}
+
void ql_mpi_work(struct work_struct *work)
{
struct ql_adapter *qdev =
container_of(work, struct ql_adapter, mpi_work.work);
struct mbox_params mbc;
struct mbox_params *mbcp = &mbc;
- mbcp->out_count = 1;
- while (ql_read32(qdev, STS) & STS_PI) {
- if (ql_get_mb_sts(qdev, mbcp)) {
- QPRINTK(qdev, DRV, ERR,
- "Could not read MPI, resetting ASIC!\n");
- ql_queue_asic_error(qdev);
- }
+ mutex_lock(&qdev->mpi_mutex);
- switch (mbcp->mbox_out[0]) {
- case AEN_LINK_UP:
- ql_link_up(qdev, mbcp);
- break;
- case AEN_LINK_DOWN:
- ql_link_down(qdev, mbcp);
- break;
- case AEN_FW_INIT_DONE:
- ql_init_fw_done(qdev, mbcp);
- break;
- case MB_CMD_STS_GOOD:
- break;
- case AEN_FW_INIT_FAIL:
- case AEN_SYS_ERR:
- case MB_CMD_STS_ERR:
- ql_queue_fw_error(qdev);
- default:
- /* Clear the MPI firmware status. */
- ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
- break;
- }
+ while (ql_read32(qdev, STS) & STS_PI) {
+ memset(mbcp, 0, sizeof(struct mbox_params));
+ mbcp->out_count = 1;
+ ql_mpi_handler(qdev, mbcp);
}
+
+ mutex_unlock(&qdev->mpi_mutex);
ql_enable_completion_interrupt(qdev, 0);
}
{
struct ql_adapter *qdev =
container_of(work, struct ql_adapter, mpi_reset_work.work);
- QPRINTK(qdev, DRV, ERR,
- "Enter, qdev = %p..\n", qdev);
- ql_write32(qdev, CSR, CSR_CMD_SET_RST);
- msleep(50);
- ql_write32(qdev, CSR, CSR_CMD_CLR_RST);
+ ql_soft_reset_mpi_risc(qdev);
}
#define SIS900_MODULE_NAME "sis900"
#define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
-static char version[] __devinitdata =
-KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
+static const char version[] __devinitconst =
+ KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
static int max_interrupt_work = 40;
static int multicast_filter_limit = 128;
#define FIRMWARE_TX "adaptec/starfire_tx.bin"
/* These identify the driver base version and may not be removed. */
-static char version[] =
+static const char version[] __devinitconst =
KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
#endif
/* These identify the driver base version and may not be removed. */
-static char version[] =
-KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
+static const char version[] __devinitconst =
+ KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE
+ " Written by Donald Becker\n";
MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
#include "de4x5.h"
-static const char version[] __devinitdata =
+static const char version[] __devinitconst =
KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
#define c_char const char
/* Global variable declaration ----------------------------- */
static int __devinitdata printed_version;
-static char version[] __devinitdata =
+static const char version[] __devinitconst =
KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
DRV_VERSION " (" DRV_RELDATE ")\n";
/* Global variable declaration ----------------------------- */
static int __devinitdata printed_version;
-static char version[] __devinitdata =
+static const char version[] __devinitconst =
KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
DRV_VERSION " (" DRV_RELDATE ")\n";
#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
/* These identify the driver base version and may not be removed. */
-static const char version[] __initdata =
-KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
-KERN_INFO " http://www.scyld.com/network/drivers.html\n";
+static const char version[] __initconst =
+ KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) "
+ DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
+ KERN_INFO " http://www.scyld.com/network/drivers.html\n";
MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
#include <linux/dmi.h>
/* These identify the driver base version and may not be removed. */
-static char version[] __devinitdata =
-KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
+static const char version[] __devinitconst =
+ KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE
+ " Written by Donald Becker\n";
/* This driver was written to use PCI memory space. Some early versions
of the Rhine may only work correctly with I/O space accesses. */
.notifier_call = lapbeth_device_event,
};
-static const char banner[] __initdata =
+static const char banner[] __initconst =
KERN_INFO "LAPB Ethernet driver version 0.02\n";
static int __init lapbeth_init_driver(void)
#include <asm/io.h>
/* These identify the driver base version and may not be removed. */
-static char version[] __devinitdata =
-KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
-KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
+static const char version[] __devinitconst =
+ KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
+ KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
projects / karo-tx-linux.git / commitdiff