ARM: dts: apq8064: add i2c sleep pinctrl states.

This patch adds missing i2c pinctrl sleep states.
Also add 16mA drive strength to the pins so that we can detect wide
range of i2c devices on the other side of level shifters.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index c711acaa39386a22c41569d5d9b9c2971c862de7..ce15c674690feda0287fbd642e7ca02354d052ad 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -19,6 +19,24 @@
                        pins = "gpio20", "gpio21";
                        function = "gsbi1";
                };
+
+               pinconf {
+                       pins = "gpio20", "gpio21";
+                       drive-strength = <16>;
+                       bias-disable;
+               };
+       };
+
+       i2c1_pins_sleep: i2c1_pins_sleep {
+               mux {
+                       pins = "gpio20", "gpio21";
+                       function = "gpio";
+               };
+               pinconf {
+                       pins = "gpio20", "gpio21";
+                       drive-strength = <2>;
+                       bias-disable = <0>;
+               };
        };
 
        i2c3_pins: i2c3 {
@@ -26,6 +44,24 @@
                        pins = "gpio8", "gpio9";
                        function = "gsbi3";
                };
+
+               pinconf {
+                       pins = "gpio8", "gpio9";
+                       drive-strength = <16>;
+                       bias-disable;
+               };
+       };
+
+       i2c3_pins_sleep: i2c3_pins_sleep {
+               mux {
+                       pins = "gpio8", "gpio9";
+                       function = "gpio";
+               };
+               pinconf {
+                       pins = "gpio8", "gpio9";
+                       drive-strength = <2>;
+                       bias-disable = <0>;
+               };
        };
 
        gsbi6_uart_2pins: gsbi6_uart_2pins {

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index ec11d4b30d02427c7a58ac8d5a3a7ab7e45d088e..7ed7999f4cb18109542251c35cf97bab929feee6 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -227,8 +227,8 @@
 
                        gsbi1_i2c: i2c@12460000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
-                               pinctrl-0 = <&i2c1_pins>;
-                               pinctrl-names = "default";
+                               pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>;
+                               pinctrl-names = "default", "sleep";
                                reg = <0x12460000 0x1000>;
                                interrupts = <0 194 IRQ_TYPE_NONE>;
                                clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
@@ -274,8 +274,8 @@
                        ranges;
                        gsbi3_i2c: i2c@16280000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
-                               pinctrl-0 = <&i2c3_pins>;
-                               pinctrl-names = "default";
+                               pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>;
+                               pinctrl-names = "default", "sleep";
                                reg = <0x16280000 0x1000>;
                                interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
                                clocks = <&gcc GSBI3_QUP_CLK>,