PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port

All platforms using Rockchip use a common clock for the Root Port and the
slot connected to it. Indicate this by setting the Slot Clock Configuration
(PCI_EXP_LNKSTA_SLC) bit in the Root Port's Link Status.

Per the Implementation Note in the spec (PCIe r3.1, sec 7.8.7), if the
downstream component also sets PCI_EXP_LNKSTA_SLC, software may set the
Common Clock Configuration (PCI_EXP_LNKCTL_CCC) bits on both ends of the
Link. This is done by pcie_aspm_configure_common_clock().

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: jeffy.chen <jeffy.chen@rock-chips.com>

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index a7467212ea18f6c792766a177582088739ce7df5..94feb7dfd8f4f454e4887042865c3f60fb478525 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -598,7 +598,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 
        /* Set RC's clock architecture as common clock */
        status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
-       status |= PCI_EXP_LNKCTL_CCC;
+       status |= PCI_EXP_LNKSTA_SLC << 16;
        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
 
        /* Set RC's RCB to 128 */