CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+ CLKDEV_CON_ID("pioA", &pioABCD_clk),
+ CLKDEV_CON_ID("pioB", &pioABCD_clk),
+ CLKDEV_CON_ID("pioC", &pioABCD_clk),
+ CLKDEV_CON_ID("pioD", &pioABCD_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{
.id = AT91CAP9_ID_PIOABCD,
.regbase = AT91CAP9_BASE_PIOA,
- .clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
.regbase = AT91CAP9_BASE_PIOB,
- .clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
.regbase = AT91CAP9_BASE_PIOC,
- .clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
.regbase = AT91CAP9_BASE_PIOD,
- .clock = &pioABCD_clk,
}
};
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+ CLKDEV_CON_ID("pioA", &pioA_clk),
+ CLKDEV_CON_ID("pioB", &pioB_clk),
+ CLKDEV_CON_ID("pioC", &pioC_clk),
+ CLKDEV_CON_ID("pioD", &pioD_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{
.id = AT91RM9200_ID_PIOA,
.regbase = AT91RM9200_BASE_PIOA,
- .clock = &pioA_clk,
}, {
.id = AT91RM9200_ID_PIOB,
.regbase = AT91RM9200_BASE_PIOB,
- .clock = &pioB_clk,
}, {
.id = AT91RM9200_ID_PIOC,
.regbase = AT91RM9200_BASE_PIOC,
- .clock = &pioC_clk,
}, {
.id = AT91RM9200_ID_PIOD,
.regbase = AT91RM9200_BASE_PIOD,
- .clock = &pioD_clk,
}
};
CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+ CLKDEV_CON_ID("pioA", &pioA_clk),
+ CLKDEV_CON_ID("pioB", &pioB_clk),
+ CLKDEV_CON_ID("pioC", &pioC_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{
.id = AT91SAM9260_ID_PIOA,
.regbase = AT91SAM9260_BASE_PIOA,
- .clock = &pioA_clk,
}, {
.id = AT91SAM9260_ID_PIOB,
.regbase = AT91SAM9260_BASE_PIOB,
- .clock = &pioB_clk,
}, {
.id = AT91SAM9260_ID_PIOC,
.regbase = AT91SAM9260_BASE_PIOC,
- .clock = &pioC_clk,
}
};
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
+ CLKDEV_CON_ID("pioA", &pioA_clk),
+ CLKDEV_CON_ID("pioB", &pioB_clk),
+ CLKDEV_CON_ID("pioC", &pioC_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{
.id = AT91SAM9261_ID_PIOA,
.regbase = AT91SAM9261_BASE_PIOA,
- .clock = &pioA_clk,
}, {
.id = AT91SAM9261_ID_PIOB,
.regbase = AT91SAM9261_BASE_PIOB,
- .clock = &pioB_clk,
}, {
.id = AT91SAM9261_ID_PIOC,
.regbase = AT91SAM9261_BASE_PIOC,
- .clock = &pioC_clk,
}
};
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+ CLKDEV_CON_ID("pioA", &pioA_clk),
+ CLKDEV_CON_ID("pioB", &pioB_clk),
+ CLKDEV_CON_ID("pioC", &pioCDE_clk),
+ CLKDEV_CON_ID("pioD", &pioCDE_clk),
+ CLKDEV_CON_ID("pioE", &pioCDE_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{
.id = AT91SAM9263_ID_PIOA,
.regbase = AT91SAM9263_BASE_PIOA,
- .clock = &pioA_clk,
}, {
.id = AT91SAM9263_ID_PIOB,
.regbase = AT91SAM9263_BASE_PIOB,
- .clock = &pioB_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.regbase = AT91SAM9263_BASE_PIOC,
- .clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.regbase = AT91SAM9263_BASE_PIOD,
- .clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.regbase = AT91SAM9263_BASE_PIOE,
- .clock = &pioCDE_clk,
}
};
CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
+ CLKDEV_CON_ID("pioA", &pioA_clk),
+ CLKDEV_CON_ID("pioB", &pioB_clk),
+ CLKDEV_CON_ID("pioC", &pioC_clk),
+ CLKDEV_CON_ID("pioD", &pioDE_clk),
+ CLKDEV_CON_ID("pioE", &pioDE_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{
.id = AT91SAM9G45_ID_PIOA,
.regbase = AT91SAM9G45_BASE_PIOA,
- .clock = &pioA_clk,
}, {
.id = AT91SAM9G45_ID_PIOB,
.regbase = AT91SAM9G45_BASE_PIOB,
- .clock = &pioB_clk,
}, {
.id = AT91SAM9G45_ID_PIOC,
.regbase = AT91SAM9G45_BASE_PIOC,
- .clock = &pioC_clk,
}, {
.id = AT91SAM9G45_ID_PIODE,
.regbase = AT91SAM9G45_BASE_PIOD,
- .clock = &pioDE_clk,
}, {
.id = AT91SAM9G45_ID_PIODE,
.regbase = AT91SAM9G45_BASE_PIOE,
- .clock = &pioDE_clk,
}
};
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+ CLKDEV_CON_ID("pioA", &pioA_clk),
+ CLKDEV_CON_ID("pioB", &pioB_clk),
+ CLKDEV_CON_ID("pioC", &pioC_clk),
+ CLKDEV_CON_ID("pioD", &pioD_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{
.id = AT91SAM9RL_ID_PIOA,
.regbase = AT91SAM9RL_BASE_PIOA,
- .clock = &pioA_clk,
}, {
.id = AT91SAM9RL_ID_PIOB,
.regbase = AT91SAM9RL_BASE_PIOB,
- .clock = &pioB_clk,
}, {
.id = AT91SAM9RL_ID_PIOC,
.regbase = AT91SAM9RL_BASE_PIOC,
- .clock = &pioC_clk,
}, {
.id = AT91SAM9RL_ID_PIOD,
.regbase = AT91SAM9RL_BASE_PIOD,
- .clock = &pioD_clk,
}
};
struct at91_gpio_bank {
unsigned short id; /* peripheral ID */
unsigned long regbase; /* offset from system peripheral base */
- struct clk *clock; /* associated clock */
};
extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
extern void __init at91_gpio_irq_setup(void);
struct at91_gpio_chip *next; /* Bank sharing same clock */
struct at91_gpio_bank *bank; /* Bank definition */
void __iomem *regbase; /* Base of register bank */
+ struct clk *clock; /* associated clock */
};
#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
}
static struct at91_gpio_chip gpio_chip[] = {
- AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
- AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
- AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
- AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
- AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
+ AT91_GPIO_CHIP("pioA", 0x00 + PIN_BASE, 32),
+ AT91_GPIO_CHIP("pioB", 0x20 + PIN_BASE, 32),
+ AT91_GPIO_CHIP("pioC", 0x40 + PIN_BASE, 32),
+ AT91_GPIO_CHIP("pioD", 0x60 + PIN_BASE, 32),
+ AT91_GPIO_CHIP("pioE", 0x80 + PIN_BASE, 32),
};
static int gpio_banks;
__raw_writel(wakeups[i], pio + PIO_IER);
if (!wakeups[i])
- clk_disable(gpio_chip[i].bank->clock);
+ clk_disable(gpio_chip[i].clock);
else {
#ifdef CONFIG_PM_DEBUG
printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
void __iomem *pio = gpio_chip[i].regbase;
if (!wakeups[i])
- clk_enable(gpio_chip[i].bank->clock);
+ clk_enable(gpio_chip[i].clock);
__raw_writel(wakeups[i], pio + PIO_IDR);
__raw_writel(backups[i], pio + PIO_IER);
continue;
}
+ at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
+ if (!at91_gpio->clock) {
+ pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
+ continue;
+ }
+
/* enable PIO controller's clock */
- clk_enable(at91_gpio->bank->clock);
+ clk_enable(at91_gpio->clock);
/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
if (last && last->bank->id == at91_gpio->bank->id)