* lowest possible freq.
*/
org_arm_podf = __raw_readl(MXC_CCM_CACRR);
+ /* Need to enable PLL1 before setting its rate. */
+ clk_enable(pll1);
+ clk_set_rate(pll1,
+ cpu_op_tbl[cpu_op_nr - 1].pll_lpm_rate);
div = clk_get_rate(pll1) /
cpu_op_tbl[cpu_op_nr - 1].cpu_rate;
reg = __raw_writel(org_arm_podf, MXC_CCM_CACRR);
while (__raw_readl(MXC_CCM_CDHIPR))
;
+ clk_disable(pll1);
}
high_bus_freq_mode = 1;
low_bus_freq_mode = 0;
.cpu_voltage = 1200000,},
{
.pll_rate = 396000000,
+ .pll_lpm_rate = 792000000,
.cpu_rate = 396000000,
.cpu_podf = 0,
.pu_voltage = 1050000,
.cpu_voltage = 1100000,},
{
.pll_rate = 396000000,
+ .pll_lpm_rate = 792000000,
.cpu_rate = 198000000,
.cpu_podf = 1,
.pu_voltage = 1050000,
.cpu_voltage = 1200000,},
{
.pll_rate = 396000000,
+ .pll_lpm_rate = 792000000,
.cpu_rate = 396000000,
.cpu_podf = 0,
.pu_voltage = 1050000,
.cpu_voltage = 1100000,},
{
.pll_rate = 396000000,
+ .pll_lpm_rate = 792000000,
.cpu_rate = 198000000,
.cpu_podf = 1,
.pu_voltage = 1050000,