drm/tegra: dc: Unify enabling the display controller

Previously output drivers would enable continuous display mode and power
up the display controller at various points during the initialization.
This is suboptimal because it accesses display controller registers in
output drivers and duplicates a bit of code.

Move this code into the display controller driver and enable the display
controller as the final step of the ->mode_set_nofb() implementation.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 0cceabd11798ec16474933dbc94fa03624f62886..3aaa84ae26811fb8c731a89e76b91297b1ff3bf3 100644 (file)
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1236,6 +1236,18 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
                value &= ~INTERLACE_ENABLE;
                tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
        }
+
+       value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
+       value &= ~DISP_CTRL_MODE_MASK;
+       value |= DISP_CTRL_MODE_C_DISPLAY;
+       tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
+
+       value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
+       value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
+                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
+       tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
+
+       tegra_dc_commit(dc);
 }
 
 static void tegra_crtc_prepare(struct drm_crtc *crtc)

diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 6875885a2dca5bfe0c573552ebc817c4248c44ad..ed970f62290306e5c78158f9600211d51251dc78 100644 (file)
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -824,16 +824,6 @@ static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
        value |= DSI_ENABLE;
        tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 
-       value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
-       value &= ~DISP_CTRL_MODE_MASK;
-       value |= DISP_CTRL_MODE_C_DISPLAY;
-       tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
-
-       value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
-       value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
-                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
-       tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
-
        tegra_dc_commit(dc);
 
        /* enable DSI controller */

diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 07771956cc94cdde276df82f85af422e35e5b5c0..7e06657ae58bc1eb2202e7da6c193eb4c8ca862b 100644 (file)
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -1022,16 +1022,6 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
        value |= HDMI_ENABLE;
        tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 
-       value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
-       value &= ~DISP_CTRL_MODE_MASK;
-       value |= DISP_CTRL_MODE_C_DISPLAY;
-       tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
-
-       value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
-       value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
-                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
-       tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
-
        tegra_dc_commit(dc);
 
        /* TODO: add HDCP support */

diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index 0c8b458b2364e751f1c9cada8ccdf3a31686d447..7cd833f5b5b591257da40c04efc209057ec62549 100644 (file)
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -168,16 +168,6 @@ static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder,
        value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
        tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
 
-       value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
-       value &= ~DISP_CTRL_MODE_MASK;
-       value |= DISP_CTRL_MODE_C_DISPLAY;
-       tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
-
-       value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
-       value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
-                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
-       tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
-
        tegra_dc_commit(rgb->dc);
 
        if (output->panel)
@@ -193,6 +183,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
                drm_panel_disable(output->panel);
 
        tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
+       tegra_dc_commit(rgb->dc);
 
        if (output->panel)
                drm_panel_unprepare(output->panel);

diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index e813df71e30cebedbf5f468a5f1ac322a8c061b0..2afe478ded3ba78e215f678f0ecd0ce09f520755 100644 (file)
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -261,17 +261,8 @@ static int tegra_sor_attach(struct tegra_sor *sor)
 
 static int tegra_sor_wakeup(struct tegra_sor *sor)
 {
-       struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
        unsigned long value, timeout;
 
-       /* enable display controller outputs */
-       value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
-       value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
-                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
-       tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
-
-       tegra_dc_commit(dc);
-
        timeout = jiffies + msecs_to_jiffies(250);
 
        /* wait for head to wake up */
@@ -1112,18 +1103,6 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
                goto unlock;
        }
 
-       /* start display controller in continuous mode */
-       value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
-       value |= WRITE_MUX;
-       tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
-
-       tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
-       tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
-
-       value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
-       value &= ~WRITE_MUX;
-       tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
-
        /*
         * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
         * raster, associate with display controller)
@@ -1198,11 +1177,13 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
                goto unlock;
        }
 
+       tegra_sor_update(sor);
+
        value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
        value |= SOR_ENABLE;
        tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 
-       tegra_sor_update(sor);
+       tegra_dc_commit(dc);
 
        err = tegra_sor_attach(sor);
        if (err < 0) {