ARM: dts: qcom: Update msm8660 device trees

* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
  should be per cpu, not part of the container
* Add GSBI node and configuration of GSBI controller

Signed-off-by: Kumar Gala <galak@codeaurora.org>

diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 169bad90dac965640039c181cd4ab67cf7c8bec2..45180adfadf1907a2b448aafca8517889014d786 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -3,4 +3,14 @@
 / {
        model = "Qualcomm MSM8660 SURF";
        compatible = "qcom,msm8660-surf", "qcom,msm8660";
+
+       soc {
+               gsbi@19c00000 {
+                       status = "ok";
+                       qcom,mode = <GSBI_PROT_I2C_UART>;
+                       serial@19c40000 {
+                               status = "ok";
+                       };
+               };
+       };
 };

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index c52a9e964a44b6bf5fca8339456070083037d073..53837aaa2f726a523d73791ca52f687528621862 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -3,6 +3,7 @@
 /include/ "skeleton.dtsi"
 
 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
 
 / {
        model = "Qualcomm MSM8660";
@@ -12,16 +13,18 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "qcom,scorpion";
-               enable-method = "qcom,gcc-msm8660";
 
                cpu@0 {
+                       compatible = "qcom,scorpion";
+                       enable-method = "qcom,gcc-msm8660";
                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
                };
 
                cpu@1 {
+                       compatible = "qcom,scorpion";
+                       enable-method = "qcom,gcc-msm8660";
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
@@ -33,55 +36,73 @@
                };
        };
 
-       intc: interrupt-controller@2080000 {
-               compatible = "qcom,msm-8660-qgic";
-               interrupt-controller;
-               #interrupt-cells = <3>;
-               reg = < 0x02080000 0x1000 >,
-                     < 0x02081000 0x1000 >;
-       };
+       soc: soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               compatible = "simple-bus";
 
-       timer@2000000 {
-               compatible = "qcom,scss-timer", "qcom,msm-timer";
-               interrupts = <1 0 0x301>,
-                            <1 1 0x301>,
-                            <1 2 0x301>;
-               reg = <0x02000000 0x100>;
-               clock-frequency = <27000000>,
-                                 <32768>;
-               cpu-offset = <0x40000>;
-       };
+               intc: interrupt-controller@2080000 {
+                       compatible = "qcom,msm-8660-qgic";
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       reg = < 0x02080000 0x1000 >,
+                             < 0x02081000 0x1000 >;
+               };
 
-       msmgpio: gpio@800000 {
-               compatible = "qcom,msm-gpio";
-               reg = <0x00800000 0x4000>;
-               gpio-controller;
-               #gpio-cells = <2>;
-               ngpio = <173>;
-               interrupts = <0 16 0x4>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-       };
+               timer@2000000 {
+                       compatible = "qcom,scss-timer", "qcom,msm-timer";
+                       interrupts = <1 0 0x301>,
+                                    <1 1 0x301>,
+                                    <1 2 0x301>;
+                       reg = <0x02000000 0x100>;
+                       clock-frequency = <27000000>,
+                                         <32768>;
+                       cpu-offset = <0x40000>;
+               };
 
-       gcc: clock-controller@900000 {
-               compatible = "qcom,gcc-msm8660";
-               #clock-cells = <1>;
-               #reset-cells = <1>;
-               reg = <0x900000 0x4000>;
-       };
+               msmgpio: gpio@800000 {
+                       compatible = "qcom,msm-gpio";
+                       reg = <0x00800000 0x4000>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpio = <173>;
+                       interrupts = <0 16 0x4>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
 
-       serial@19c40000 {
-               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-               reg = <0x19c40000 0x1000>,
-                     <0x19c00000 0x1000>;
-               interrupts = <0 195 0x0>;
-               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
-               clock-names = "core", "iface";
-       };
+               gcc: clock-controller@900000 {
+                       compatible = "qcom,gcc-msm8660";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       reg = <0x900000 0x4000>;
+               };
+
+               gsbi12: gsbi@19c00000 {
+                       compatible = "qcom,gsbi-v1.0.0";
+                       reg = <0x19c00000 0x100>;
+                       clocks = <&gcc GSBI12_H_CLK>;
+                       clock-names = "iface";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
 
-       qcom,ssbi@500000 {
-               compatible = "qcom,ssbi";
-               reg = <0x500000 0x1000>;
-               qcom,controller-type = "pmic-arbiter";
+                       serial@19c40000 {
+                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                               reg = <0x19c40000 0x1000>,
+                                     <0x19c00000 0x1000>;
+                               interrupts = <0 195 0x0>;
+                               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
+                               clock-names = "core", "iface";
+                               status = "disabled";
+                       };
+               };
+
+               qcom,ssbi@500000 {
+                       compatible = "qcom,ssbi";
+                       reg = <0x500000 0x1000>;
+                       qcom,controller-type = "pmic-arbiter";
+               };
        };
 };