The base address of exception vectors.
config ARM_PATCH_PHYS_VIRT
- --- bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
- --- depends on EXPERIMENTAL
- - bool "Patch physical to virtual translations at runtime"
+++++ + bool "Patch physical to virtual translations at runtime" if EMBEDDED
+++++ + default y
depends on !XIP_KERNEL && MMU
depends on !ARCH_REALVIEW || !SPARSEMEM
help
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_AUX_CTRL_MASK 0xc0000fff
++++ ++#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
++++ ++#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
++++ ++#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
++++ ++#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
++++ ++#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
++++ ++#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
++++ ++#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
++++ ++#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
- -----#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17)
+ +++++#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27