clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+ clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
+ clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
+ clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
+ clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
+ clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[esdhc_a_podf], 200000000);
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
+ #include <linux/of_device.h>
-#include <mach/nand.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
/*
* This is a device driver for the NAND flash controller found on the
#include <linux/err.h>
#include <asm/io.h>
#include <asm/sizes.h>
- #include <mach/hardware.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
- #include <asm/io.h>
-
#include <plat/regs-nand.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
- #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
- static int hardware_ecc = 1;
- #else
- static int hardware_ecc = 0;
- #endif
-
- #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
- static const int clock_stop = 1;
- #else
- static const int clock_stop = 0;
- #endif
-
-
/* new oob placement block for use with hardware ecc generation
*/