m68knommu: make ColdFire IMR and IPR register definitions absolute addresses

Make all definitions of the ColdFire Interrupt Mask and Pending registers
absolute addresses. Currently some are relative to the MBAR peripheral region.

The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.

This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 69722366b084bc10e34c2d1ef9a01b78fdd146a2..e8bae33aed6052d6c2a6a5704cd927b99d0afd70 100644 (file)
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -40,8 +40,8 @@
 #define        MCFSIM_ICR15            0x22            /* Intr Ctrl reg 15 (r/w) */
 #endif
 
-#define MCFSIM_IMR             0x36            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_IPR             0x3a            /* Interrupt Pend reg (r/w) */
+#define        MCFSIM_IMR              (MCF_MBAR + 0x36)       /* Interrupt Mask */
+#define        MCFSIM_IPR              (MCF_MBAR + 0x3a)       /* Interrupt Pending */
 
 #define        MCFSIM_RSR              0x40            /* Reset Status reg (r/w) */
 #define        MCFSIM_SYPCR            0x41            /* System Protection reg (r/w)*/

diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 7f0c2c3660fd15b986db84e59a2f067b003a1835..d0aa7f27a311dc7551a0f4e47240faae7b882c29 100644 (file)
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -32,9 +32,9 @@
 #define        MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
 #define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
 #define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define        MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define        MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define        MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
+#define        MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define        MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define        MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
 #define        MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
 #define        MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
 #define        MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */

diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index 6da24f6539027066aea0b96f27fe19f6f659bc21..0d6d192355ca02b36db648d49be28052d68aa369 100644 (file)
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -31,8 +31,8 @@
 #define MCFSIM_SWIVR           0x02            /* SW Watchdog intr reg (r/w) */
 #define MCFSIM_SWSR            0x03            /* SW Watchdog service (r/w) */
 #define MCFSIM_MPARK           0x0C            /* BUS Master Control Reg*/
-#define MCFSIM_IPR             0x40            /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR             0x44            /* Interrupt Mask reg (r/w) */
+#define MCFSIM_IPR             (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define MCFSIM_IMR             (MCF_MBAR + 0x44)       /* Interrupt Mask */
 #define MCFSIM_ICR0            0x4c            /* Intr Ctrl reg 0 (r/w) */
 #define MCFSIM_ICR1            0x4d            /* Intr Ctrl reg 1 (r/w) */
 #define MCFSIM_ICR2            0x4e            /* Intr Ctrl reg 2 (r/w) */

diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index a58f1760d858f6f1e9499bede581d07849bd4df6..378a6d971eed2b4fa7c03e9980a7928a03e13893 100644 (file)
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -32,10 +32,10 @@
 #define        MCFSIM_ICR3             0x28            /* Intr Ctrl reg 3 (r/w) */
 #define        MCFSIM_ICR4             0x2c            /* Intr Ctrl reg 4 (r/w) */
 
-#define MCFSIM_ISR             0x30            /* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR            0x34            /* Interrupt Transition (r/w) */
-#define        MCFSIM_PIWR             0x38            /* Interrupt Wakeup reg (r/w) */
-#define        MCFSIM_PIVR             0x3f            /* Interrupt Vector reg (r/w( */
+#define        MCFSIM_ISR              (MCF_MBAR + 0x30)       /* Intr Source */
+#define        MCFSIM_PITR             (MCF_MBAR + 0x34)       /* Intr Transition */
+#define        MCFSIM_PIWR             (MCF_MBAR + 0x38)       /* Intr Wakeup */
+#define        MCFSIM_PIVR             (MCF_MBAR + 0x3f)       /* Intr Vector */
 
 #define        MCFSIM_WRRR             0x280           /* Watchdog reference (r/w) */
 #define        MCFSIM_WIRR             0x284           /* Watchdog interrupt (r/w) */

diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 3bc3adaa7ee0138f7438090dae100c1b85ed8b87..255f7f3120d96271fc9275510eba84da6dd2efee 100644 (file)
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -31,9 +31,9 @@
 #define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
 #define        MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
 #define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define        MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define        MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define        MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
+#define        MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pend */
+#define        MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define        MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
 #define        MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
 #define        MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
 #define        MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */

diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 79f58dd6a83da3d532d3687d139144999daf3801..afdd56325ae7ccce6b1eb8c10b19718093d603f8 100644 (file)
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -31,9 +31,9 @@
 #define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
 #define        MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
 #define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
-#define        MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
-#define        MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
-#define        MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
+#define        MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
+#define        MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
+#define        MCFSIM_AVR              (MCF_MBAR + 0x4b)       /* Autovector Ctrl */
 #define        MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
 #define        MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
 #define        MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */

diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index 5c0c150b40671c7b5af644fa176493574b6958b5..cce2574203885412b9c5f742405928f74fb0ae3b 100644 (file)
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
 void mcf_setimr(int index)
 {
        u16 imr;
-       imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-       __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+       imr = __raw_readw(MCFSIM_IMR);
+       __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
        u16 imr;
-       imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
-       __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+       imr = __raw_readw(MCFSIM_IMR);
+       __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
        u16 imr;
-       imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
+       imr = __raw_readw(MCFSIM_IMR);
        imr |= mask;
-       __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
+       __raw_writew(imr, MCFSIM_IMR);
 }
 
 #else
@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
 void mcf_setimr(int index)
 {
        u32 imr;
-       imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-       __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
+       imr = __raw_readl(MCFSIM_IMR);
+       __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_clrimr(int index)
 {
        u32 imr;
-       imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
-       __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
+       imr = __raw_readl(MCFSIM_IMR);
+       __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
 }
 
 void mcf_maskimr(unsigned int mask)
 {
        u32 imr;
-       imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
+       imr = __raw_readl(MCFSIM_IMR);
        imr |= mask;
-       __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
+       __raw_writel(imr, MCFSIM_IMR);
 }
 
 #endif
@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
 #ifdef MCFSIM_AVR
        if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
                u8 avec;
-               avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
+               avec = __raw_readb(MCFSIM_AVR);
                avec |= (0x1 << (irq - EIRQ1 + 1));
-               __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
+               __raw_writeb(avec, MCFSIM_AVR);
        }
 #endif
 }