#define PARM_DMA_CACHE_DEF 0
/* RX defines */
-#define USE_FBR0 true
-
-#ifdef USE_FBR0
-/* #define FBR0_BUFFER_SIZE 256 */
-#endif
-
-/* #define FBR1_BUFFER_SIZE 2048 */
+#define USE_FBR0 1
#define FBR_CHUNKS 32
/* number of RFDs - default and min */
#ifdef USE_FBR0
#define RFD_LOW_WATER_MARK 40
-#define NIC_MIN_NUM_RFD 64
#define NIC_DEFAULT_NUM_RFD 1024
+#define NUM_FBRS 2
#else
#define RFD_LOW_WATER_MARK 20
-#define NIC_MIN_NUM_RFD 64
#define NIC_DEFAULT_NUM_RFD 256
+#define NUM_FBRS 1
#endif
+#define NIC_MIN_NUM_RFD 64
+
#define NUM_PACKETS_HANDLED 256
#define ALCATEL_BAD_STATUS 0xe47f0000
};
/*
- * Structure for look-up table holding free buffer ring pointers
+ * Structure for look-up table holding free buffer ring pointers, addresses
+ * and state.
*/
struct fbr_lookup {
- void *virt[MAX_DESC_PER_RING_RX];
- void *buffer1[MAX_DESC_PER_RING_RX];
- void *buffer2[MAX_DESC_PER_RING_RX];
- u32 bus_high[MAX_DESC_PER_RING_RX];
- u32 bus_low[MAX_DESC_PER_RING_RX];
+ void *virt[MAX_DESC_PER_RING_RX];
+ void *buffer1[MAX_DESC_PER_RING_RX];
+ void *buffer2[MAX_DESC_PER_RING_RX];
+ u32 bus_high[MAX_DESC_PER_RING_RX];
+ u32 bus_low[MAX_DESC_PER_RING_RX];
+ void *ring_virtaddr;
+ dma_addr_t ring_physaddr;
+ void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ uint64_t real_physaddr;
+ uint64_t offset;
+ u32 local_full;
+ u32 num_entries;
+ u32 buffsize;
};
/*
* reference(s) to the rings
*/
struct rx_ring {
-#ifdef USE_FBR0
- void *fbr0_ring_virtaddr;
- dma_addr_t fbr0_ring_physaddr;
- void *fbr0_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- dma_addr_t fbr0_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- uint64_t fbr0_real_physaddr;
- uint64_t fbr0_offset;
- u32 local_fbr0_full;
- u32 fbr0_num_entries;
- u32 fbr0_buffsize;
-#endif
- void *fbr1_ring_virtaddr;
- dma_addr_t fbr1_ring_physaddr;
- void *fbr1_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- dma_addr_t fbr1_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- uint64_t fbr1_real_physaddr;
- uint64_t fbr1_offset;
- struct fbr_lookup *fbr[2]; /* One per ring */
- u32 local_fbr1_full;
- u32 fbr1_num_entries;
- u32 fbr1_buffsize;
+ struct fbr_lookup *fbr[NUM_FBRS];
void *ps_ring_virtaddr;
dma_addr_t ps_ring_physaddr;
if (adapter->registry_jumbo_packet < 2048) {
#ifdef USE_FBR0
- rx_ring->fbr0_buffsize = 256;
- rx_ring->fbr0_num_entries = 512;
+ rx_ring->fbr[0]->buffsize = 256;
+ rx_ring->fbr[0]->num_entries = 512;
#endif
- rx_ring->fbr1_buffsize = 2048;
- rx_ring->fbr1_num_entries = 512;
+ rx_ring->fbr[1]->buffsize = 2048;
+ rx_ring->fbr[1]->num_entries = 512;
} else if (adapter->registry_jumbo_packet < 4096) {
#ifdef USE_FBR0
- rx_ring->fbr0_buffsize = 512;
- rx_ring->fbr0_num_entries = 1024;
+ rx_ring->fbr[0]->buffsize = 512;
+ rx_ring->fbr[0]->num_entries = 1024;
#endif
- rx_ring->fbr1_buffsize = 4096;
- rx_ring->fbr1_num_entries = 512;
+ rx_ring->fbr[1]->buffsize = 4096;
+ rx_ring->fbr[1]->num_entries = 512;
} else {
#ifdef USE_FBR0
- rx_ring->fbr0_buffsize = 1024;
- rx_ring->fbr0_num_entries = 768;
+ rx_ring->fbr[0]->buffsize = 1024;
+ rx_ring->fbr[0]->num_entries = 768;
#endif
- rx_ring->fbr1_buffsize = 16384;
- rx_ring->fbr1_num_entries = 128;
+ rx_ring->fbr[1]->buffsize = 16384;
+ rx_ring->fbr[1]->num_entries = 128;
}
#ifdef USE_FBR0
- adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr0_num_entries +
- adapter->rx_ring.fbr1_num_entries;
+ adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[0]->num_entries +
+ adapter->rx_ring.fbr[1]->num_entries;
#else
- adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr1_num_entries;
+ adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[1]->num_entries;
#endif
/* Allocate an area of memory for Free Buffer Ring 1 */
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr1_num_entries) + 0xfff;
- rx_ring->fbr1_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff;
+ rx_ring->fbr[1]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
bufsize,
- &rx_ring->fbr1_ring_physaddr);
- if (!rx_ring->fbr1_ring_virtaddr) {
+ &rx_ring->fbr[1]->ring_physaddr);
+ if (!rx_ring->fbr[1]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 1\n");
return -ENOMEM;
* are ever returned, make sure the high part is retrieved here
* before storing the adjusted address.
*/
- rx_ring->fbr1_real_physaddr = rx_ring->fbr1_ring_physaddr;
+ rx_ring->fbr[1]->real_physaddr = rx_ring->fbr[1]->ring_physaddr;
/* Align Free Buffer Ring 1 on a 4K boundary */
et131x_align_allocated_memory(adapter,
- &rx_ring->fbr1_real_physaddr,
- &rx_ring->fbr1_offset, 0x0FFF);
+ &rx_ring->fbr[1]->real_physaddr,
+ &rx_ring->fbr[1]->offset, 0x0FFF);
- rx_ring->fbr1_ring_virtaddr =
- (void *)((u8 *) rx_ring->fbr1_ring_virtaddr +
- rx_ring->fbr1_offset);
+ rx_ring->fbr[1]->ring_virtaddr =
+ (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
+ rx_ring->fbr[1]->offset);
#ifdef USE_FBR0
/* Allocate an area of memory for Free Buffer Ring 0 */
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr0_num_entries) + 0xfff;
- rx_ring->fbr0_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff;
+ rx_ring->fbr[0]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
bufsize,
- &rx_ring->fbr0_ring_physaddr);
- if (!rx_ring->fbr0_ring_virtaddr) {
+ &rx_ring->fbr[0]->ring_physaddr);
+ if (!rx_ring->fbr[0]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 0\n");
return -ENOMEM;
* are ever returned, make sure the high part is retrieved here before
* storing the adjusted address.
*/
- rx_ring->fbr0_real_physaddr = rx_ring->fbr0_ring_physaddr;
+ rx_ring->fbr[0]->real_physaddr = rx_ring->fbr[0]->ring_physaddr;
/* Align Free Buffer Ring 0 on a 4K boundary */
et131x_align_allocated_memory(adapter,
- &rx_ring->fbr0_real_physaddr,
- &rx_ring->fbr0_offset, 0x0FFF);
+ &rx_ring->fbr[0]->real_physaddr,
+ &rx_ring->fbr[0]->offset, 0x0FFF);
- rx_ring->fbr0_ring_virtaddr =
- (void *)((u8 *) rx_ring->fbr0_ring_virtaddr +
- rx_ring->fbr0_offset);
+ rx_ring->fbr[0]->ring_virtaddr =
+ (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
+ rx_ring->fbr[0]->offset);
#endif
- for (i = 0; i < (rx_ring->fbr1_num_entries / FBR_CHUNKS); i++) {
+ for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
u64 fbr1_offset;
u64 fbr1_tmp_physaddr;
u32 fbr1_align;
* the size of FBR0. By allocating N buffers at once, we
* reduce this overhead.
*/
- if (rx_ring->fbr1_buffsize > 4096)
+ if (rx_ring->fbr[1]->buffsize > 4096)
fbr1_align = 4096;
else
- fbr1_align = rx_ring->fbr1_buffsize;
+ fbr1_align = rx_ring->fbr[1]->buffsize;
fbr_chunksize =
- (FBR_CHUNKS * rx_ring->fbr1_buffsize) + fbr1_align - 1;
- rx_ring->fbr1_mem_virtaddrs[i] =
+ (FBR_CHUNKS * rx_ring->fbr[1]->buffsize) + fbr1_align - 1;
+ rx_ring->fbr[1]->mem_virtaddrs[i] =
pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr1_mem_physaddrs[i]);
+ &rx_ring->fbr[1]->mem_physaddrs[i]);
- if (!rx_ring->fbr1_mem_virtaddrs[i]) {
+ if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
"Could not alloc memory\n");
return -ENOMEM;
}
/* See NOTE in "Save Physical Address" comment above */
- fbr1_tmp_physaddr = rx_ring->fbr1_mem_physaddrs[i];
+ fbr1_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
et131x_align_allocated_memory(adapter,
&fbr1_tmp_physaddr,
* access later
*/
rx_ring->fbr[1]->virt[index] =
- (u8 *) rx_ring->fbr1_mem_virtaddrs[i] +
- (j * rx_ring->fbr1_buffsize) + fbr1_offset;
+ (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
+ (j * rx_ring->fbr[1]->buffsize) + fbr1_offset;
/* now store the physical address in the descriptor
* so the device can access it
rx_ring->fbr[1]->bus_low[index] =
(u32) fbr1_tmp_physaddr;
- fbr1_tmp_physaddr += rx_ring->fbr1_buffsize;
+ fbr1_tmp_physaddr += rx_ring->fbr[1]->buffsize;
rx_ring->fbr[1]->buffer1[index] =
rx_ring->fbr[1]->virt[index];
#ifdef USE_FBR0
/* Same for FBR0 (if in use) */
- for (i = 0; i < (rx_ring->fbr0_num_entries / FBR_CHUNKS); i++) {
+ for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
u64 fbr0_offset;
u64 fbr0_tmp_physaddr;
fbr_chunksize =
- ((FBR_CHUNKS + 1) * rx_ring->fbr0_buffsize) - 1;
- rx_ring->fbr0_mem_virtaddrs[i] =
+ ((FBR_CHUNKS + 1) * rx_ring->fbr[0]->buffsize) - 1;
+ rx_ring->fbr[0]->mem_virtaddrs[i] =
pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr0_mem_physaddrs[i]);
+ &rx_ring->fbr[0]->mem_physaddrs[i]);
- if (!rx_ring->fbr0_mem_virtaddrs[i]) {
+ if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
"Could not alloc memory\n");
return -ENOMEM;
}
/* See NOTE in "Save Physical Address" comment above */
- fbr0_tmp_physaddr = rx_ring->fbr0_mem_physaddrs[i];
+ fbr0_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
et131x_align_allocated_memory(adapter,
&fbr0_tmp_physaddr,
&fbr0_offset,
- rx_ring->fbr0_buffsize - 1);
+ rx_ring->fbr[0]->buffsize - 1);
for (j = 0; j < FBR_CHUNKS; j++) {
u32 index = (i * FBR_CHUNKS) + j;
rx_ring->fbr[0]->virt[index] =
- (u8 *) rx_ring->fbr0_mem_virtaddrs[i] +
- (j * rx_ring->fbr0_buffsize) + fbr0_offset;
+ (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
+ (j * rx_ring->fbr[0]->buffsize) + fbr0_offset;
rx_ring->fbr[0]->bus_high[index] =
(u32) (fbr0_tmp_physaddr >> 32);
rx_ring->fbr[0]->bus_low[index] =
(u32) fbr0_tmp_physaddr;
- fbr0_tmp_physaddr += rx_ring->fbr0_buffsize;
+ fbr0_tmp_physaddr += rx_ring->fbr[0]->buffsize;
rx_ring->fbr[0]->buffer1[index] =
rx_ring->fbr[0]->virt[index];
}
/* Free Free Buffer Ring 1 */
- if (rx_ring->fbr1_ring_virtaddr) {
+ if (rx_ring->fbr[1]->ring_virtaddr) {
/* First the packet memory */
for (index = 0; index <
- (rx_ring->fbr1_num_entries / FBR_CHUNKS); index++) {
- if (rx_ring->fbr1_mem_virtaddrs[index]) {
+ (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
+ if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
u32 fbr1_align;
- if (rx_ring->fbr1_buffsize > 4096)
+ if (rx_ring->fbr[1]->buffsize > 4096)
fbr1_align = 4096;
else
- fbr1_align = rx_ring->fbr1_buffsize;
+ fbr1_align = rx_ring->fbr[1]->buffsize;
bufsize =
- (rx_ring->fbr1_buffsize * FBR_CHUNKS) +
+ (rx_ring->fbr[1]->buffsize * FBR_CHUNKS) +
fbr1_align - 1;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr1_mem_virtaddrs[index],
- rx_ring->fbr1_mem_physaddrs[index]);
+ rx_ring->fbr[1]->mem_virtaddrs[index],
+ rx_ring->fbr[1]->mem_physaddrs[index]);
- rx_ring->fbr1_mem_virtaddrs[index] = NULL;
+ rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
}
}
/* Now the FIFO itself */
- rx_ring->fbr1_ring_virtaddr = (void *)((u8 *)
- rx_ring->fbr1_ring_virtaddr - rx_ring->fbr1_offset);
+ rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
+ rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr1_num_entries)
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries)
+ 0xfff;
pci_free_consistent(adapter->pdev, bufsize,
- rx_ring->fbr1_ring_virtaddr,
- rx_ring->fbr1_ring_physaddr);
+ rx_ring->fbr[1]->ring_virtaddr,
+ rx_ring->fbr[1]->ring_physaddr);
- rx_ring->fbr1_ring_virtaddr = NULL;
+ rx_ring->fbr[1]->ring_virtaddr = NULL;
}
#ifdef USE_FBR0
/* Now the same for Free Buffer Ring 0 */
- if (rx_ring->fbr0_ring_virtaddr) {
+ if (rx_ring->fbr[0]->ring_virtaddr) {
/* First the packet memory */
for (index = 0; index <
- (rx_ring->fbr0_num_entries / FBR_CHUNKS); index++) {
- if (rx_ring->fbr0_mem_virtaddrs[index]) {
+ (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
+ if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
bufsize =
- (rx_ring->fbr0_buffsize *
+ (rx_ring->fbr[0]->buffsize *
(FBR_CHUNKS + 1)) - 1;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr0_mem_virtaddrs[index],
- rx_ring->fbr0_mem_physaddrs[index]);
+ rx_ring->fbr[0]->mem_virtaddrs[index],
+ rx_ring->fbr[0]->mem_physaddrs[index]);
- rx_ring->fbr0_mem_virtaddrs[index] = NULL;
+ rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
}
}
/* Now the FIFO itself */
- rx_ring->fbr0_ring_virtaddr = (void *)((u8 *)
- rx_ring->fbr0_ring_virtaddr - rx_ring->fbr0_offset);
+ rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
+ rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr0_num_entries)
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries)
+ 0xfff;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr0_ring_virtaddr,
- rx_ring->fbr0_ring_physaddr);
+ rx_ring->fbr[0]->ring_virtaddr,
+ rx_ring->fbr[0]->ring_physaddr);
- rx_ring->fbr0_ring_virtaddr = NULL;
+ rx_ring->fbr[0]->ring_virtaddr = NULL;
}
#endif
rx_local->local_psr_full = 0;
/* Now's the best time to initialize FBR1 contents */
- fbr_entry = (struct fbr_desc *) rx_local->fbr1_ring_virtaddr;
- for (entry = 0; entry < rx_local->fbr1_num_entries; entry++) {
+ fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
+ for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
fbr_entry->word2 = entry;
/* Set the address and parameters of Free buffer ring 1 (and 0 if
* required) into the 1310's registers
*/
- writel((u32) (rx_local->fbr1_real_physaddr >> 32),
+ writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
&rx_dma->fbr1_base_hi);
- writel((u32) rx_local->fbr1_real_physaddr, &rx_dma->fbr1_base_lo);
- writel(rx_local->fbr1_num_entries - 1, &rx_dma->fbr1_num_des);
+ writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr1_base_lo);
+ writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr1_num_des);
writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
/* This variable tracks the free buffer ring 1 full position, so it
* has to match the above.
*/
- rx_local->local_fbr1_full = ET_DMA10_WRAP;
+ rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
writel(
- ((rx_local->fbr1_num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+ ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
&rx_dma->fbr1_min_des);
#ifdef USE_FBR0
/* Now's the best time to initialize FBR0 contents */
- fbr_entry = (struct fbr_desc *) rx_local->fbr0_ring_virtaddr;
- for (entry = 0; entry < rx_local->fbr0_num_entries; entry++) {
+ fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
+ for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
fbr_entry->word2 = entry;
fbr_entry++;
}
- writel((u32) (rx_local->fbr0_real_physaddr >> 32),
+ writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
&rx_dma->fbr0_base_hi);
- writel((u32) rx_local->fbr0_real_physaddr, &rx_dma->fbr0_base_lo);
- writel(rx_local->fbr0_num_entries - 1, &rx_dma->fbr0_num_des);
+ writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr0_base_lo);
+ writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr0_num_des);
writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
/* This variable tracks the free buffer ring 0 full position, so it
* has to match the above.
*/
- rx_local->local_fbr0_full = ET_DMA10_WRAP;
+ rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
writel(
- ((rx_local->fbr0_num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+ ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
&rx_dma->fbr0_min_des);
#endif
*/
if (
#ifdef USE_FBR0
- (ring_index == 0 && buff_index < rx_local->fbr0_num_entries) ||
+ (ring_index == 0 && buff_index < rx_local->fbr[0]->num_entries) ||
#endif
- (ring_index == 1 && buff_index < rx_local->fbr1_num_entries)) {
+ (ring_index == 1 && buff_index < rx_local->fbr[1]->num_entries)) {
spin_lock_irqsave(&adapter->fbr_lock, flags);
if (ring_index == 1) {
struct fbr_desc *next =
- (struct fbr_desc *) (rx_local->fbr1_ring_virtaddr) +
- INDEX10(rx_local->local_fbr1_full);
+ (struct fbr_desc *) (rx_local->fbr[1]->ring_virtaddr) +
+ INDEX10(rx_local->fbr[1]->local_full);
/* Handle the Free Buffer Ring advancement here. Write
* the PA / Buffer Index for the returned buffer into
next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
next->word2 = buff_index;
- writel(bump_free_buff_ring(&rx_local->local_fbr1_full,
- rx_local->fbr1_num_entries - 1),
+ writel(bump_free_buff_ring(&rx_local->fbr[1]->local_full,
+ rx_local->fbr[1]->num_entries - 1),
&rx_dma->fbr1_full_offset);
}
#ifdef USE_FBR0
else {
struct fbr_desc *next = (struct fbr_desc *)
- rx_local->fbr0_ring_virtaddr +
- INDEX10(rx_local->local_fbr0_full);
+ rx_local->fbr[0]->ring_virtaddr +
+ INDEX10(rx_local->fbr[0]->local_full);
/* Handle the Free Buffer Ring advancement here. Write
* the PA / Buffer Index for the returned buffer into
next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
next->word2 = buff_index;
- writel(bump_free_buff_ring(&rx_local->local_fbr0_full,
- rx_local->fbr0_num_entries - 1),
+ writel(bump_free_buff_ring(
+ &rx_local->fbr[0]->local_full,
+ rx_local->fbr[0]->num_entries - 1),
&rx_dma->fbr0_full_offset);
}
#endif
/* Setup the receive dma configuration register for normal operation */
u32 csr = 0x2000; /* FBR1 enable */
- if (adapter->rx_ring.fbr1_buffsize == 4096)
+ if (adapter->rx_ring.fbr[1]->buffsize == 4096)
csr |= 0x0800;
- else if (adapter->rx_ring.fbr1_buffsize == 8192)
+ else if (adapter->rx_ring.fbr[1]->buffsize == 8192)
csr |= 0x1000;
- else if (adapter->rx_ring.fbr1_buffsize == 16384)
+ else if (adapter->rx_ring.fbr[1]->buffsize == 16384)
csr |= 0x1800;
#ifdef USE_FBR0
csr |= 0x0400; /* FBR0 enable */
- if (adapter->rx_ring.fbr0_buffsize == 256)
+ if (adapter->rx_ring.fbr[0]->buffsize == 256)
csr |= 0x0100;
- else if (adapter->rx_ring.fbr0_buffsize == 512)
+ else if (adapter->rx_ring.fbr[0]->buffsize == 512)
csr |= 0x0200;
- else if (adapter->rx_ring.fbr0_buffsize == 1024)
+ else if (adapter->rx_ring.fbr[0]->buffsize == 1024)
csr |= 0x0300;
#endif
writel(csr, &adapter->regs->rxdma.csr);
#ifdef USE_FBR0
if (ring_index > 1 ||
(ring_index == 0 &&
- buff_index > rx_local->fbr0_num_entries - 1) ||
+ buff_index > rx_local->fbr[0]->num_entries - 1) ||
(ring_index == 1 &&
- buff_index > rx_local->fbr1_num_entries - 1))
+ buff_index > rx_local->fbr[1]->num_entries - 1))
#else
- if (ring_index != 1 || buff_index > rx_local->fbr1_num_entries - 1)
+ if (ring_index != 1 || buff_index > rx_local->fbr[1]->num_entries - 1)
#endif
{
/* Illegal buffer or ring index cannot be used by S/W*/