ENGR00237452 i.MX6:IEEE1588: disable phy Ar8031 SmartEEE

Connecting two boards directly more than 2 hours, Ar8031 phy link
status generates glitch, which cause ethernet link down/up issue, but
ethernet still be active. There have three cases to validate the issue:

Item#1: If add performance stress test while runing IEEE1588, the link
	down/up issue cannot be found.
Item#2: If insert switch between two net nodes and run IEEE1588 test,
	the issue also cannot be found.
Item#3: If disable AR8031 SmartEEE feature, after two days overnight test,
	no such issue found.

The issue is caused by phy Ar8031 SmartEEE feature, Item#1 and Item#2 can
prevent phy enter lpm mode, which match the Item#3 test result, so disable
SmartEEE feature to avoid the link issue generation.

Signed-off-by: Fugang Duan  <B38611@freescale.com>

diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
index b1c8eaa165357ce4defcff4639984907b14d7bd1..1e42f4f2193a821d147c5a9f6896bb7afaac3c4c 100644 (file)
--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
@@ -336,6 +336,16 @@ static int mx6_arm2_fec_phy_init(struct phy_device *phydev)
 {
        unsigned short val;
 
+       /* Ar8031 phy SmartEEE feature cause link status generates glitch,
+        * which cause ethernet link down/up issue, so disable SmartEEE
+        */
+       phy_write(phydev, 0xd, 0x3);
+       phy_write(phydev, 0xe, 0x805d);
+       phy_write(phydev, 0xd, 0x4003);
+       val = phy_read(phydev, 0xe);
+       val &= ~(0x1 << 8);
+       phy_write(phydev, 0xe, val);
+
        /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
        phy_write(phydev, 0xd, 0x7);
        phy_write(phydev, 0xe, 0x8016);

diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index f028fa82830407c7404af357450f72956d97cec0..99db549427f7d425789d44446d6f74c8cb44a2c7 100644 (file)
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -346,6 +346,17 @@ static int mx6q_sabreauto_fec_phy_init(struct phy_device *phydev)
        unsigned short val;
 
        if (!board_is_mx6_reva()) {
+               /* Ar8031 phy SmartEEE feature cause link status generates
+                * glitch, which cause ethernet link down/up issue, so
+                * disable SmartEEE
+                */
+               phy_write(phydev, 0xd, 0x3);
+               phy_write(phydev, 0xe, 0x805d);
+               phy_write(phydev, 0xd, 0x4003);
+               val = phy_read(phydev, 0xe);
+               val &= ~(0x1 << 8);
+               phy_write(phydev, 0xe, val);
+
                /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
                phy_write(phydev, 0xd, 0x7);
                phy_write(phydev, 0xe, 0x8016);

diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c
index 986d291cf5dad284837af0263a0c16056a9619f0..56fe1d68bb901370c3e6eb20d1696c2ded5d2c91 100644 (file)
--- a/arch/arm/mach-mx6/board-mx6q_sabresd.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c
@@ -254,6 +254,16 @@ static int mx6q_sabresd_fec_phy_init(struct phy_device *phydev)
 {
        unsigned short val;
 
+       /* Ar8031 phy SmartEEE feature cause link status generates glitch,
+        * which cause ethernet link down/up issue, so disable SmartEEE
+        */
+       phy_write(phydev, 0xd, 0x3);
+       phy_write(phydev, 0xe, 0x805d);
+       phy_write(phydev, 0xd, 0x4003);
+       val = phy_read(phydev, 0xe);
+       val &= ~(0x1 << 8);
+       phy_write(phydev, 0xe, val);
+
        /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
        phy_write(phydev, 0xd, 0x7);
        phy_write(phydev, 0xe, 0x8016);