When setting up an encoder channel, the setup value includes a polarity
and direction, but these are the same bit of the setup value:
S626_CLKPOL_POS = S626_CNTDIR_UP = 0
S626_CLKPOL_NEG = S626_CNTDIR_DOWN = 1
In the construction of the setup value, both the CLKPOL and the CNTDIR
constants are shifted by the same amount `S626_BF_CLKPOL`. Only the
following combinations are set up currently (this may change if user
configuration of the encoder is implemented properly):
(S626_CLKPOL_POS << S626_BF_CLKPOL)
(S626_CLKPOL_POS << S626_BF_CLKPOL) |
(S626_CNTDIR_UP << S626_BF_CLKPOL)
(S626_CLKPOL_POS << S626_BF_CLKPOL) |
(S626_CNTDIR_DOWN << S626_BF_CLKPOL)
The first two are used in "counter" mode and is equivalent to:
(S626_CLKPOL_POS << S626_BF_CLKPOL)
The last one is used in "timer" mode and is equivalent to:
(S626_CNTDIR_DOWN << S626_BF_CLKPOL)
Use the shorter equivalents. The comments in "s626.h" indicate that the
'CLKPOL' constants make more sense for the "counter" mode (when the
encoders operate as up/down counters) and the 'CNTDIR' constants make
more sense for the "timer" mode.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(S626_INDXSRC_SOFT << S626_BF_INDXSRC) |
/* Operating mode is Timer. */
(S626_CLKSRC_TIMER << S626_BF_CLKSRC) |
- /* Active high clock. */
- (S626_CLKPOL_POS << S626_BF_CLKPOL) |
/* Count direction is Down. */
(S626_CNTDIR_DOWN << S626_BF_CLKPOL) |
/* Clock multiplier is 1x. */
(S626_CLKSRC_COUNTER << S626_BF_CLKSRC) |
/* Active high clock. */
(S626_CLKPOL_POS << S626_BF_CLKPOL) |
- /* Count direction is up. */
- (S626_CNTDIR_UP << S626_BF_CLKPOL) |
/* Clock multiplier is 1x. */
(S626_CLKMULT_1X << S626_BF_CLKMULT) |
/* Enabled by index */