PCI: Support PCIe Capability Slot registers only for ports with slots

Previously we allowed callers to access Slot Capabilities, Status, and
Control for Root Ports even if the Root Port did not implement a slot.
This seems dubious because the spec only requires these registers if a
slot is implemented.

It's true that even Root Ports without slots must have *space* for these
slot registers, because the Root Capabilities, Status, and Control
registers are after the slot registers in the capability.  However,
for a v1 PCIe Capability, the *semantics* of the slot registers are
undefined unless a slot is implemented.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Jiang Liu <jiang.liu@huawei.com>

diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 9a46fa9135d98d844d6ba84500d492f7b8b8d500..061da8c3ab4b84bb35c3278d2a867e154d70533a 100644 (file)
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -497,9 +497,9 @@ static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
 {
        int type = pci_pcie_type(dev);
 
-       return type == PCI_EXP_TYPE_ROOT_PORT ||
-              (type == PCI_EXP_TYPE_DOWNSTREAM &&
-               pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT);
+       return (type == PCI_EXP_TYPE_ROOT_PORT ||
+               type == PCI_EXP_TYPE_DOWNSTREAM) &&
+              pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
 }
 
 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)